This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow.

H.264/AVC is a new video compression standard designed for future broadband network. Compared with former video coding standards such as MPEG-2 and MPEG-4 part 2, it saves up to 40% in bit rate and provides important characteristics such as error resilience, stream switching etc. However, the improvement in performance also introduces increase in computational complexity, which requires more powerful hardware. At the same time, there are several image and video coding standards currently used such as JPEG and MPEG-4. Although ASIC design meets the performance requirement, it lacks flexibility for heterogeneous standards. Hence reconfigurable DSP processor is more suitable for media processing since it provides both real-time performance and flexibility. Currently there are several single scalar DSP processors in the market. Compare to media processor, which is generally SIMD or VLIW, single scalar DSP is cheaper and has smaller area while its performance for video processing is limited. In this paper, a method to promote the performance of single scalar DSP by attaching hardware accelerators is proposed. And the bottleneck for performance promotion is investigated and the upper limit of acceleration of a certain single scalar DSP for H.264/AVC decoding is presented. Behavioral model of H.264/AVC decoder is realized in pure software during the first step. Although real-time performance cannot be achieved with pure software implementation, computational complexity of different parts is investigated and the critical path in decoding was exposed by analyzing the first design of this software solution. Then both functional acceleration and addressing acceleration were investigated and designed to achieve the performance for real-time decoding using available clock frequency within 200MHz.

Les maladies infectieuses représentent aujourd’hui un problème majeur de santé publique. Devant l’augmentation des résistances bactériennes, l’émergence de nouveaux pathogènes et la propagation rapide de l’épidémie, le suivi et la surveillance de la transmission de la maladie devient particulièrement importants. Face à une telle menace, la société doit se préparer à l'avance pour réagir rapidement et efficacement si une telle épidémie est déclarée. Cela nécessite une mise en place des dispositifs de suivi et de prévention. Dans ce contexte, nous nous intéressons, dans le présent travail, à l’élaboration d’un Système d’Information Décisionnel Spatio-temporel pour le suivi et la surveillance du phénomène de propagation de l’épidémie de la grippe saisonnière au sein de la population de la ville d’Oran (Algérie). L’objectif de ce système est double : il consiste, d’une part, à comprendre comment l’épidémie se propage par l’utilisation du réseau social Small World (SW) et du modèle à compartiments d’épidémie SEIR (Susceptible-Exposed-Infected-Removed), et d’autre part, à stocker dans un entrepôt les données multiples tout en les analysant par un outil d’analyse en ligne de donnée Spatiale dit SOLAP (Spatial On-Line Analytical Processing). / Today, infectious diseases represent a major public health problem. With the increase of bacterial resistance, the emergence of new pathogens and the rapid spread of epidemic, monitoring and surveillance of disease transmission becomes important. In the face of such a threat, the society must prepare in advance to respond quickly and effectively if an outbreak is declared. This requires setting up monitoring mechanisms and prevention.In this context, we are particularly interested by development a Spatiotemporal decision support system for monitoring and preventing the phenomenon of seasonal influenza epidemic spread in the population of Oran (city at Algeria).The objective of this system is twofold: on one hand, to understand how epidemic is spreading through the social network by using SEIR (Susceptible-Exposed-Infected-Removed) compartmental model within Small World network, and on the other hand, to store multiple data in data warehouse and analyzing it by a specific online analysis tool Spatial OLAP (Spatial on-line Analytical Processing).

The master thesis focuses on more efficient application of Scrum methodology in a development team within specific company. The thesis takes an advantage from the SW-CMM philosophy applied in agile environment in order to achieve better effectivity. Theorethical base is utilized for a comparison with current state in the company described in analytical part. Proposals for a solution of current situation are based on drawback detection. Proposals are subject for risk analysis followed by precaution. Costs of proposals implementation with included precautions are evaluated in economic evaluation part. This part also contains benefits of proposals.

This thesis deals with design and implementing of a tool for development of MPSoC (multiprocessor systems on chip). It is going to apprise the reader with this matter and introduces several ways how to solve these issues in Codasip Studio IDE (integrated development environment). The graphical editor for multicore system development and a set of support tools for fast and effective development are introduced in this thesis. These are mainly interactive wizards which help user to start new projects. To handle the subject matter it is necessary to understand CodAL language, Eclipse IDE, GMF (Graphical Modeling Framework) and EMF (Eclipse Modeling Framework) which are used for graphical editor implementation.

The master's theses deal with concept and creation of a new version of the compute kernel in expert system based on NPS32. This paper is focused on possibilities and requirements of the expert system's operation on the Internet, too. One part of the study is devoted to testing the designed SW and demonstrating of its facilities.

This study evaluated the use of the Prevent-Teach-Reinforce for Secondary (PTR-SEC) model as an individualized Tier 3 intervention within the School-Wide Positive Behavioral Interventions and Supports (SW-PBIS) in three high school classrooms. Three teaching staff (two teachers and one instructional aide) and three students with autism spectrum disorders participated in the study. The study examined the degree to which the classroom staff implemented the PTR intervention plan with fidelity and its impact on the students’ behaviors, using a multiple baseline across participants design. The results indicated that the teaching staff implemented the PTR intervention plan with high levels of fidelity, and their implementation of the intervention plan led to decreases in problem behavior and increases in replacement behavior across all three participating students with ASD. The PTR-SEC teams found the PTR-SEC intervention to be acceptable and satisfactory; all three staff expressed interest in continuing to implement the PTR intervention plan after completion of the study.

This project deals with the PC diagnostics, creation of SW and HW audits and development of information system for storage and analysis of data gained. The system is designed for Microsoft Windows operation system. Part of the system called Client is developed in C/C++ programming language. To gather diagnostic data, the WMI interface is used. The web part of information system is created using PHP scripting language and database MySQL server.

Microcontrollers, the brains of embedded systems, have found their way into every aspect of our lives including medical devices such as pacemakers. Pacemakers provide life supporting functions to people therefore it is critical for these devices to meet their timing constraints. This thesis examines the use of hardware co-processing to accelerate the calculation time associated with the critical tasks of a pacemaker. In particular, we use an FPGA to accelerate a microcontroller’s calculation time of the Kendall Tau Rank Correlation Coefficient algorithm. The Kendall Tau Rank Correlation Coefficient is a statistical measure that determines the pacemaker’s voltage level for heart stimulation. This thesis explores three different hardware distributions of this algorithm between an FPGA and a pacemaker’s microcontroller. The first implementation uses one microcontroller to establish the baseline performance of the system. The next implementation executes the entire Kendall Tau algorithm on an FPGA with varying degrees of parallelism. The final implementation of the Kendall Tau algorithm splits the computational requirements between the microcontroller and FPGA. This thesis uses these implementations to compare system-level issues such as power consumption and other tradeoffs that arise when using an FPGA for co-processing.

Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain. As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server. / QC 20101118