Low dimensional nanostructures have defined the frontier of the research in material science for the last two decades. Presented here are the results of experimental research on growth, device fabrication and application of quasi-one dimensional phthalocyanines and metal oxides to gas-sensing. The possibility of rational tuning of the growth conditions, in order to control composition, morphology, size, orientation and alignment of the grown low-dimensional nanostructures was investigated. Employing custom designed heating stages coupled with optical microscope the in situ approach of monitoring the growth of nanostructures has been realized. Using this method, the growth of VO2 nanowires and nanoplatelets have been investigated and two novel growth mechanisms were discovered and explained. A variety of phthalocyanine and metal-oxide nanowire-based chemical sensors have been proposed, fabricated and tested. The focus of our research was on the development of new sensing principles and the improvement of existing ones. In particular, nanowires of tin and titanium dioxide were proposed to be used as self-heated chemiresistors capable of operating in the absence of an external heater, thus paving the way for ultra-low power consumption sensors. For the first time VO2 nanowires were used to create a nano-Pirani gauge and a gas sensor employing a sharp temperature-driven metal-insulator transition in this material. The sensor is sensitive to both chemically active and inert gases. Its performance is modeled and optimization parameters are presented.

High electron mobility transistors (HEMTs) have long been studied for high frequency and high-power application. Among widely known high electron mobility transistors, AlGaN/GaN HEMTs are having the upper hand due to high electron mobility of the GaN channel. Over the times, issues like current collapse, gate leakage, self-heating and gate lag have questioned the performance and reliability of these devices. In the recent years, engineers have come up with newer architectures to address some of these issues. Inserting a high-k dielectric oxide layer in the gate stack proved to be an effective solution to mitigate gate leakage, reduce interfacial traps and improve optimal working conditions. This work aims to study the reliability aspect of these so-called metal-oxide-semiconductor high electron mobility transistors (MOS-HEMT) specifically, HfO2 and HfZrO2 MOS-HEMTs. It was found through numerical simulations that though HfO2 and HfZrO2 dielectrics were able to mitigate gate leakage current, they tend to accumulate more heat in the channel region with respect to the conventional silicon nitride (SiN) passivated counterparts. Moreover, few asymmetric structures were proposed where silicon nitride was placed in the dielectric layer along with HfO2/HfZrO2. In this study it was found that these asymmetric structures showed superior thermal performance while showing near-zero gate leakage current.

Dans la première partie on propose un outil mathématique pour traiter les conditions aux limites dynamiques d'un problème couplé d'EDP. La simulation avec des conditions aux limites dynamiques nécessite quelques fois une condition de "switch" en temps des conditions aux limites de Dirichlet en Neumann. La méthode numérique (St DN) a été validée avec des mesures expérimentales pour le cas de la contamination croisée en industrie micro-électronique. Cet outil sera utilisé par la suite pour simuler le phénomène de « self-heating » dans les polymères et les hydrogels sous sollicitations dynamiques. Dans la deuxième partie, on s'intéresse à la modélisation du phénomène de self-heating dans les polymères, les hydrogels et les tissus biologiques. D'abord, nous nous sommes focalisés sur la modélisation de la loi constitutive de l'hydrogel de type HEMA-EGDMA. Nous avons utilisé la théorie des invariants polynomiaux pour définir la loi constitutive du matériau. Ensuite, nous avons mis en place un modèle théorique en thermomécanique couplée d'un milieu continu classique pour analyser la production de chaleur dans ce matériau. Deux potentiels thermodynamiques ont été proposés et identifiés avec les mesures expérimentales. Une nouvelle forme d'équation du mouvement non-linéaire et couplée a été obtenue (un système d'équation aux dérivées partielles parabolique et hyperbolique non-linéaire couplé avec des conditions aux limites dynamiques). Dans la troisième partie, une méthode numérique des équations thermomécaniques (couplage parabolique-hyperbolique) pour les modèles a été utilisée. Cette étape nous a permis, entre autres, de résoudre ce système couplé. La méthode est basée sur la méthode des éléments finis. Divers résultats expérimentaux obtenus sur ce phénomène de self-heating sont présentés dans ce travail suivi d'une étude de corrélations des résultats théoriques et expérimentaux. Dans la dernière partie de ce travail, ces divers résultats sont repris et leurs conséquences sur la modélisation du comportement de l'hydrogel naturel utilisé dans le domaine biomédical sont discutées. / In the first part, we propose a mathematical tool for treating the dynamic boundary conditions. The simulation within dynamic boundary condition requires sometimes ''switch'' condition in time of the Dirichlet to Neumann boundary condition (St DN). We propose a numerical method validated with experimental measurements for the case of cross-contamination in microelectronics industry. This tool will be used to compute self-heating in the polymers and hydrogels under dynamic loading. In the second part we focus on modeling the self-heating phenomenon in polymers, hydrogels and biological tissues. We develop constitutive law of the hydrogel type HEMA-EGDMA, focusing on the heat e.ects (dissipation) in this material. Then we set up a theoretical model of coupled thermo-mechanical classic continuum for a better understanding of the heat production in this media. We use polynomial invariants theory to define the constitutive law of the media. Two original thermodynamic potentials are proposed. Original non-linear and coupled governing equations were obtained and identified with the experimental measurements (non-linear parabolic-hyperbolic system with the dynamic boundary condition). In the third part, numerical methods were used to solve thermo-mechanical formalism for the model. This step deals with a numerical method of a coupled partial di.erential equation system of the self-heating (parabolic-hyperbolic coupling). Then, is step allows us, among other things, to propose an appropriate numerical methods to solve this system. The numerical method is based on the finite element methods. Numerous experimental results on the self-heating phenomenon are presented in this work together with correlations studies between the theoretical and experimental results. In the last part of the thesis, these various results will be presented and their impact on the modeling of the behavior of the natural hydrogel used in the biomedical field will be discussed.

The complementary metal-oxide-semiconductor (CMOS) scaling process of the recent decades, coupled with new device structures and materials, has aggravated thermal problems and turned them into major reliability issues for deeply-scaled devices. As a consequence, the thermal transport dynamic and its impact on the device performance at submicron dimensions is established as a contemporary theme. In this context, a new selfconsistent electro-thermal particle-based device simulator for the study of self-heating effects in p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) based in silicon is developed and presented. The electrical module of the tool utilizes the Ensemble Monte Carlo method to perform the charge transport, whereas the thermal module evaluates the non-isothermal temperature profiles by solving the phonon energy balance equations for both acoustic and optical phonon baths. These temperature profiles are fed back into the electrical module, which adjusts the carriers’ scattering rate accordingly, thus, properly accounting for the device current capability degradation. The developed tool proved to be suitable for sub-100 nm device simulations, and it was used to perform relevant case study simulations of 24-nm channel length bulk and fully-depleted siliconon- insulator (FD-SOI) MOSFETs. General device parameters extracted from the simulations are qualitatively in agreement with the expected behavior, as well as data from the literature, ensuring the proper operation of the tool. Electro-thermal simulations of bulk and FD-SOI devices provided both acoustic and optical phonon temperature profiles across the transistor structure, as well as the heat generation map and the device power dissipation. Some results were also extracted via Joule heating thermal model, and they are presented for comparison. The current degradation due to self-heating was found to be significant for FD-SOI devices, but very modest for bulk ones. At a fixed bias point of VD =VG = 1:5 V, for instance, bulk devices presented a current variation of as much as 0:75%, whereas for FD-SOI devices it reached up to 8:82% for Tgate = 400 K. Hot spot acoustic (lattice) and optical phonon temperatures were extracted as a function of the applied bias for both topologies. The lattice temperature rise, for instance, exceeded 10 K and 150 K over the heat sink temperature for bulk and FD-SOI transistors, respectively, observing the same bias point and gate temperature presented earlier. The particle-based nature of the tool is also suitable for the study of the impact of trap activity in MOSFETs and its interplay with self-heating effects. Simulations of charge traps were used to analyze the statistical distribution of the current deviations in 25-nm bulk MOSFETs due to traps. The simulations showed that these deviations are exponentially-distributed, as experimentally observed and reported in the literature. Electro-thermal simulations of charge traps in bulk and FD-SOI transistors revealed that the largest degradation on the device current occurs when the effects of self-heating and trap activity take place simultaneously. At lower biases, the impact of charge traps dominates the current degradation, whereas the self-heating component prevails for larger biases.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.

"This paper investigates the thermal conditions at the surface and at depth of 1.8 cm (3/4-inch) maple plywood exposed to heat fluxes between 6 and 15 kW/m2 in the cone calorimeter for up to 8 hours. The minimum heat flux for unpiloted smoldering ignition was 7.5 kW/m2 and compared favorably to classical self-heating theory. The role of self-heating was explored via temperature measurements distributed within the specimens. Elevated subsurface temperature profiles indicated self-heating was an important ignition factor resulting in ignition at depth with smolder propagation to the surface and into the material. The ignition depth was shown to be a function of the heat flux with the depth moving towards the surface as the heat flux increased. Supporting work included sensor calibration testing, mass loss rate analysis, char depth testing and computer modeling. The calibration testing showed optical pyrometer temperature measurements compare favorably to those of surface mounted thermocouples. Mass loss rate analysis was found to be a lagging indicator of smoldering ignition. The char depth tests showed that the rate of change of the temperatures recorded at depth increased around the time the derived char front passed. Computer modeling (HEATING) of a heat flux applied to the plywood for conditions similar to the performed ignition tests compared favorably to experimental data for sub-critical incident heat flux temperature profiles, excepting surface temperatures. For heat fluxes near critical, the model correctly predicted thermal runaway below the sample surface. At higher heat fluxes simulation results indicated surface ignition at times significantly earlier than experimental results."

An accumulated combustible dust layer on some hot process equipment such as dryers or hot bearings can be ignited and result in fires when the hot surface temperature is sufficiently high. The ASTM E 2021 test procedure is often used to determine the Hot Surface Minimum Ignition Temperature for a half inch deep layer of a particular dust material. This test procedure was used in this thesis to study possible effects of combustible liquid (such as lubricating oil) and powder additives in the dust layer as well as air flow effects. The following combustible dusts were used: paper dust from a printing press, Arabic gum powder, Pittsburgh seam coal, and brass powder. To develop an improved understanding of the heat transfer, and oxygen mass transfer phenomena occurring in the dust layer, additional instrumentation such as a second thermocouple in the dust layer, an oxygen analyzer and gas sampling line, and an air velocity probe were used in at least some tests. Hot Surface Minimum Ignition temperatures were 220oC for Pittsburgh seam coal, 360oC for paper dust, 270¡Ãƒâ€° for Arabic gum powder, and > 400oC for brass powder. The addition of 5-10 weight percent stearic acid powder resulted in significantly lower ignition temperature of brass powder. When combustible liquids were added to the dust layer, the ignition temperatures did not decrease regardless of the liquids¡¯ ignitibility because the liquids seemed to act as heat absorbents. Although air velocity on the order of 1 cm/s did not affect test results, much larger air velocities did affect the results. With 33 cm/s downward airflow at the elevation of the surface of the layer, Pittsburgh seam coal was not ignited at 230¡Ãƒâ€° which was 10¡Ãƒâ€° higher than the 220¡Ãƒâ€° hot surface ignition temperature without airflow. Based on the results and data from the additional instrumentations, modifications of the ASTM E2021 test procedure are recommended.

A novel method is shown for fitting and/or validating electro-thermal models using pulsed I(V) measurements and pulsed I(V) simulations demonstrated using modifications of an available non-linear model for an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device. After extracting the thermal time constant, good agreement is achieved between measured and simulated pulsed I(V) results under a wide range of different pulse conditions including DC, very short (<0.1%) duty cycles, and varied pulse widths between these extremes. A pulsed RF load-pull test bench was also assembled and demonstrated for a VDMOS (Vertically Diffused Metal Oxide Semiconductor) and an LDMOS power transistor. The basic technique should also be useful for GaAs and GaN transistors with suitable consideration for the complexity added by trapping mechanisms present in those types of transistors.

This thesis is mainly proposed and discussed the characteristics of polycrystalline silicon thin film transistor putting forward and probing into four kinds of novel buried-oxide structures. Because of the shortcoming of the traditional polycrystalline silicon thin film transistor, like leakage current (On/Off state current), subthreshold swing, floating body effect (kink effect), self-heating effect, and short channel effect etc.. Thus, we propose and fabricate four kinds of novel structural polycrystalline silicon thin film transistors that are involved in the following, indicating to improve the critical issues of polycrystalline silicon thin film transistor mentioned above. 1. We propose and fabricate the multiple/dual trenched-body polycrystalline silicon thin film transistor. This proposed structure is demonstrated to obviously suppress the off-state leakage up to 70% reduction, comparing with the conventional device. Also, we survey the reliability of this proposed device included temperature and DC hot-carrier stress effects. We found that the trenched-body TFTs perform more rapid degradation than the conventional TFT does after the temperature and stress durations, but their electrical characteristics are still superior to the conventional counterparts. Importantly, we demonstrate that this proposed device have a dramatic potential to be a novel capacitorless 1T-DRAM, because of its large floating-body-charge storages. As the experiment, the large threshold voltage shift is examined apparently after a certain write and erase operations, leading to a manifest programming window. 2. We propose and fabricate the block-oxide polycrystalline silicon thin film transistor. This proposed structure can not only improve the leakage issue of conventional device seriously, but also avoid fluctuating threshold voltage attributed from the ultra-thin film effect. 3. We propose and fabricate the floating-body contact polycrystalline silicon thin film transistor. This structure is modified by the conventional contact window in order to effectively improve the kink effect, utilizing the bottom gate polycrystalline silicon thin film transistor. 4. Finally, we propose and simulate the non-continuous buried layer polycrystalline silicon thin film transistor. This structure built upon the field oxidation layer can effectively improve the self-heating effect and kink effect. Furthermore, this structure is simple to fabricate, practical, and completely compatible on CMOS technology.