The advancements of semiconductor processing technology have led to the ability for computing platforms to operate on large amounts of data at very high clock speeds. To fully utilize this processing power the components must have data continually available for operation upon and transport to other system components. To enable this data requirement, high speed serial links have replaced slower parallel communication protocols. Serial interfaces inherently require fewer signals for communication and thus reduce the device pin count, area and cost. A serial communication interface can also be run at a higher frequency because the clock skew between channels is no longer an issue since the data transmitted on various channels is independent. Serial data transmission also comes with a set of drawbacks when signal integrity is considered. The data must propagate through a channel that induces unwanted effects onto the signals such as intersymbol interference. These channel effects must be understood and mitigated to successfully transmit data without creating bit errors upon reception at the target component. Previously developed adaptive equalization techniques have been used to filter the effects of intersymbol interference from the transmitted data in the signal. This report explores the modeling and implementation of a system comprised of a transmitter, channel, and receiver to understand how intersymbol interference can be removed through a decision-feedback equalizer realized in hardware. The equalizer design, implementation, and measurements are the main focus of this report and are based on previous works in the areas of integrated circuit testing, channel modeling, and equalizer design. Simulation results from a system modeled in Simulink are compared against the results from a hardware model implemented with an FPGA, analog to digital converter and discrete circuit elements. In both the software and hardware models, bit errors were eliminated for certain amounts of intersymbol interference when a receiver with decision-feedback equalization was used instead of a receiver without equalization. / text

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012

As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers’ relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully.

Motion planning for redundant manipulators poses special challenges because the required inverse kinematics are difficult and not complete. This thesis investigates and proposes methods for motion planning for these systems that do not require inverse kinematics and are potentially complete. These methods are also compared in performance to standard inverse kinematics based methods.

Jitter requirements have become more stringent with higher speed serial communication links. Reducing jitter, with the main focus on reducing data dependant jitter (DDJ), is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The adaptive FIR pre-emphasis is implemented in the IBM 7WL 0.18 µm SiGe BiCMOS process. SiGe heterojunction bipolar transistors (HBTs) provide high bandwidth, low noise devices which could reduce the total system jitter. The trade-offs between utilising metal oxide semiconductor (MOS) current mode logic (CML) and SiGe bipolar CML are also discussed in comparison with a very high fT (IBM 8HP process with fT = 200 GHz) process. A reduction in total system jitter can be achieved by keeping the sub-components of the system jitter constant while optimising the DDJ. High speed CML circuits have been employed to allow data rates in excess of 5 Gb/s to be transmitted whilst still maintaining an internal voltage swing of at least 300 mV. This allows the final FIR filter adaptation scheme to minimise the DDJ within 12.5 % of a unit interval, at a data rate of 5 Gb/s implementing 6 FIR pre-emphasis filter taps, for a worst case copper backplane channel (30" FR-4 channel). The implemented integrated circuit (IC) designed as part of the verification process takes up less than 1 mm2 of silicon real estate. In this dissertation, SPICE simulation results are presented, as well as the novel IC implementation of the proposed FIR filter adaptation technique as part of the hypothesis verification procedure. The implemented transmitter and receiver were tested for functionality, and showed the successful functional behaviour of all the implemented CML gates associated with the first filter tap. However, due to the slow charge and discharge rate of the pulse generation circuit in both the transmitter and receiver, only the main operational state of the transmitter could be experimentally validated. As a result of the adaptation scheme implemented, the contribution in this research lies in that a designer utilising such an IC can optimise the DDJ, reducing the total system jitter, and hence increasing the data fidelity with minimal effort. / Dissertation (MEng)--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

Submitted by LUCAS ARRUDA RAMALHO null (lucasarrudaramalho@gmail.com) on 2018-03-14T22:14:34Z No. of bitstreams: 1 Ramalho_Tese_2018.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) / Approved for entry into archive by Cristina Alexandra de Godoy null (cristina@adm.feis.unesp.br) on 2018-03-15T14:45:53Z (GMT) No. of bitstreams: 1 ramalho_la_dr_ilha.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) / Made available in DSpace on 2018-03-15T14:45:53Z (GMT). No. of bitstreams: 1 ramalho_la_dr_ilha.pdf: 8417019 bytes, checksum: 0b39588579fa6ac3abad291909bc4662 (MD5) Previous issue date: 2018-02-23 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplicações. O setup de hardware utilizado foi construído sobre dois bastidores ATCA com 12 placas Pulsares 2b em cada. A taxa de dados máxima atingida foi de 3.84 Tbps entre os dois bastidores ATCAs. O DSS está operacional e foi utilizado para emular o fluxo de dados de saída do CMS Silicon Outer Tracker, e auxiliar na demonstração da proposta trigger de nível 1. Esta tese descreve essa demonstração como estudo de caso, que testa o formatador de dados do trigger (downstream) através do DSS e- mulando a saída de dados do detector. Nesse estudo de caso, tanto o DSS e o trigger proposto foram implementados utilizando o mesmo hardware ATCA e a Pulsar 2b. O foco do estudo de caso é descrever a comunicação entre o Data Sourcing shelf e o Pattern Recognition shelf. O DSS atendeu aos requisitos da demonstração provendo uma interface de usuário que permite aos desenvolvedores de trigger inserir sinais de controle e executar operações de leitura e escrita de forma remota nos FPGAs. / The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is operational and was already used to emulate the CMS Silicon Tracker data, and helped the demonstration of a L1 Trigger approach. This thesis describes the demonstration performed as case of study, which used the DSS as upstream system and tested the trigger data delivery as a downstream. In the case of study, both DSS and the proposed trigger are performed by the same ATCA hardware and the Pulsar 2b. The case of study focused to describe the communication between the Data Sourcing shelf and the Pattern Recognition shelf. Data Sourcing reached those requirements for the demonstration and provided a user interface that allows the trigger developers to insert control signals or to perform W/R operations inside Pulsar 2b FPGA block memories.

Orientador: Aílton Akira Shinoda / Resumo: A evolução dos Multi Gigabit Transceivers (MGT) nos Field Programmable Gate Arrays (FPGA) trouxeram oportunidades para o desenvolvimento de sistemas de aquisição e formatadores de dados em diversas áreas. As novas famílias de FPGAs são capazes de lidar com canais de transmissão com velocidade da ordem de Gbps que utilizam protocolos seriais de alta velocidade, podendo assim se tornar o futuro dos processadores downstream ou upstream. Os sistemas digitais criados para esse propósito, precisam ser confiáveis e síncronos entre dezenas de canais e placas. Como forma de permitir o teste de projetos com essa taxa massiva de bits, essa tese descreve o desenvolvimento do Data Sourcing System (DSS). Esse sistema deve ser capaz de testar qualquer application upstream ou downstream, permitir controle e acesso remoto aos sinais internos dos FPGAs, medir sincronismo e latência entre MGTs e avaliar integridade de links através de bit error rate (BER). Este trabalho faz parte de uma colaboração internacional liderada pelo Fermilab que propôs, com a contribuição do sistema descrito nesta tese, um sistema de trigger de nível 1 para o Compact Muon Solenoid (CMS) Outer Tracker. O dectetor CMS é um experimento vinculado ao European Organization for Nuclear Research (CERN). O DSS foi implementado sobre a placa Pulsar 2b, uma placa padrão Advanced Telecommunication Computing Architecture (ATCA), desenvolvida pelo Fermilab, que conta com um dispositivo FPGA para programação e costumização de aplica... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: The evolution of Fiel Programmable Gate Array (FPGA) Multi Gigabit Transceivers (MGT) brought opportunities for data formatter and data acquisition projects in several areas. The newer FPGA families are capable of handling Gigabits per second (Gbps) I/Os implemented using high speed serial link protocols and to become the future downstream processors. The digital systems created for that purpose need to be reliable and synchronous between dozens of channels and boards. To allow the test of such massive bitrate projects, this work implemented the Data Sourcing System (DSS) e- mulator that is able to produce synchronized data in 12 boards, 480 channels, delivering up to 8 Gbps for each of them. This work is part of a international collaboration, led by Fermilab, that proposed with the contribuition of the system described in this thesis, a Level 1 (L1) tri- gger for the Compact Muon Solenoid (CMS) Outer Tracker. The CMS detector is an European Organization for Nuclear Research (CERN) experiment. The DSS is based on the Pulsar 2b, a custom Advanced Telecommunication Computing Architecture (ATCA) standard FPGA-based board designed by Fermilab to be a scalable high speed link processor system. This hardware setup was implemented at Fermilab using two interconnected ATCA shelves with 12 Pulsar 2b on both. The results show that the system is able to provide data at 3.8 Terabits per second (Tbps), and to measure synchronization, latency and bit error rate of the MGTs. The system is o... (Complete abstract click electronic access below) / Doutor