Detta ingenjörsarbete är utfört hos Syntronic Research and Development AB i Gävle och går ut på att undersöka möjligheten att separera en display-modul från sin styrande processor-krets samt att skapa ett generellt gränssnitt för att möjliggöra ett enkelt utbyte av display-moduler. Detta har genomförts genom att konstruera en prototyp, baserad på en så kallad serializer / deserializer-lösning. En förstudie har genomförts där lämpliga komponener valts ut för uppgiften och olika lösningar vägts mot varandra. En prototyp har sedan konstruerats, mönsterkort har tillverkats men tyvärr inte monterats (på grund av ett logistiskt missöde). Resultatet är, förutom ovan nämnda begränsning, en prototyp som väl uppfyller de specifikationer som anges i uppdragsbeskrivningen. Flera förslag till vidareutveckling presenteras som kan utöka funktionaliteten. / This engineering work has been conducted at Syntronic Research and Development AB in Gävle and aims to explore the possibilities of separating a display module from its controlling processor circuit and to create a general interface to allow easy replacement of display modules. This has been implemented by designing a prototype, based on a so-called serializer / deserializer solution. A pilot study has been carried out where appropriate components has been selected for the task, and various solutions have been weighted against each other. A prototype has been designed, printed circuit boards have been produced but unfortunately not mounted (because of a logistical mishap). The result is, with the above limitations, a prototype that fully satisfies the specifications outlined in the task description. Several suggestions for further development are presented, which could extend the functionality.

Post-Silicon validation of a designed ASIC is an essential step in the product development process. During the validation process, all specifications of the ASICs have to be controlled in a lab environment. Serializer/Deserialiser(SerDes) blocks in an ASIC are used to perform high-speed serial data communication between distinct integrated circuits. The goal of the thesis is to validate the power consumption of SerDes IP blocks provided by different vendors in an ASIC. To validate power consumption, current and voltage values are read from power supply lines. Then these values are digitized and stored on a Raspberry Pi. To perform these operations, the initial firmware provided by vendors is improved to control SerDes operations, and software is developed to control the Raspberry Pi. Power measured operation is performed for every possible data rate for each SerDes modules. Power measurement is also performed for different temperature range in industry standards with the highest possible data rate for each SerDes IP block. As a final step, measured power consumption values are compared to vendors’ data. / Validering av en designad ASIC efter kisel är ett viktigt steg i produktutvecklingsprocessen. Under valideringsprocessen måste alla specifikationer för ASIC kontrolleras i en laboratoriemiljö. Serializer / Deserialiser (SerDes) -block i en ASIC används för att utföra höghastighets seriell datakommunikation mellan distinkta integrerade kretsar. Målet med avhandlingen är att validera strömförbrukningen för SerDes IP-block som tillhandahålls av olika leverantörer i en ASIC. För att validera strömförbrukningen läses strömoch spänningsvärden från strömförsörjningsledningarna. Sedan digitaliseras dessa värden och lagras på en Raspberry Pi. För att utföra dessa operationer förbättras den inledande firmware som tillhandahålls av leverantörer för att styra SerDesoperationer och programvara utvecklas för att styra Raspberry Pi. Effektmätt operation utförs för varje möjlig datahastighet för varje SerDes-modul. Mätoperationer utförs också för olika temperaturintervall i branschstandarder med högsta möjliga datahastighet för varje SerDes IP-block. Som ett sista steg jämförs uppmätta energiförbrukningsvärden med leverantörens data.

<p>GRAIL is a Java library for capturing and manipulating graphs. It is used in the VizzAnalyzer reengineering tool developed at Växjö University that allows quality analysis of software systems.</p><p>GXL is a standard exchange format for software data in graph structure, mainly used within the field of software reengineering that is widely supported in other tools within the same field. It is important for VizzAnalyzer to support GXL as an exchange format to allow collaboration with other tools on this basis.</p><p>As the goal of this thesis, a GXL graph serializer/deserialize architecture for GRAIL has been developed that allows data exchange between VizzAnalyzer and other tools that support the GXL format.</p><p>VizzAnalyzer is capable of analyzing large software systems and therefore the task required special attention on high performance and low memory footprint even with large GXL graph structures.</p>

GRAIL is a Java library for capturing and manipulating graphs. It is used in the VizzAnalyzer reengineering tool developed at Växjö University that allows quality analysis of software systems. GXL is a standard exchange format for software data in graph structure, mainly used within the field of software reengineering that is widely supported in other tools within the same field. It is important for VizzAnalyzer to support GXL as an exchange format to allow collaboration with other tools on this basis. As the goal of this thesis, a GXL graph serializer/deserialize architecture for GRAIL has been developed that allows data exchange between VizzAnalyzer and other tools that support the GXL format. VizzAnalyzer is capable of analyzing large software systems and therefore the task required special attention on high performance and low memory footprint even with large GXL graph structures.

Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 65 nm CMOS technology with additional requirement of 1-V supply. This design has been implemented using Cadence IC design environment. The additional advantage of the proposed testing strategy is that it requires lower number of I/O pins and avoids the large number of high speed I/O pads. It therefore also solves the problem of the bandwidth limitation that is associated with I/O transmission paths. The design of the on-chip tester based on memory contains no analog block and is implemented entirely in digital domain. In the proposed design, low frequency of 1 MHz has been used outside the chip to load the data into the memory during the write mode. During the read mode, the frequency of 625 MHz is used to read the data from the memory. A multiplexing system is used to reuse the stored data during read mode to test the intended functionality and performance. In order to convert the parallel data into serial data at high frequency at the memory output, serializer has been used. By using the frequencies of 1.25 GHz and 2.5 GHz, the serializer speeds up the data from the lower frequency of 625 MHz to the highest frequency of 5 GHz in order to test DAC at 5 GHz.

Master's thesis is focused on designing optical converter for EMC measurement transfering signal through noisy enviroment. First part contains analysis of electromagnetic interference and its coupling and measurement, especially types of probes for interference maesurement. Next part passing through designing of optoelectric and electrooptic converter with digital intensity modulation. Last part is about realization of optical converter.