No description available.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / Designers of small airborne FQPSK-B (-B) transmitters face at least two significant challenges. First, many U.S. Department of Defense (DOD) test applications require that transmitters accommodate a continuum of data rates from 1, to at least 20 Mb/s in one design. Another challenge stems from the need to package a high-speed digital baseband signal generator in very close proximity to radio frequency (RF) circuitry required for 1.4 to 2.4 GHz operation. The -B baseband filter options prescribed by Digcom/Feher [2] are a major contributor to variable data rate design challenges. This paper summarizes a study of -B filter alternatives and introduces FQPSK-JR (JR), an alternative to -B that can simplify digital baseband transmitter designs. Very short impulse response digital filters are used to produce essentially the same spectral efficiency and nonlinear amplifier (NLA) compatibility as -B while preserving or improving detection efficiency (DE). In addition, a strategy for eliminating baseband shaping filters is briefly discussed. New signaling wavelets and, modified wavelet versus symbol sequence mapping rules associated with them, can be captured from a wide range of alternative filter designs.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / This paper will discuss the use of a specialized telemetry signal simulator for pre-mission verification of a telemetry receiving system. This will include how to configure tests that will determine system performance under “real time” conditions such as multipath fading and Doppler shifting. The paper will analyze a telemetry receiving system and define tests for each part of the system. This will include tests for verification of the antenna system. Also included, will be tests for verification of the receiver/combiner system. The paper will further discuss how adding PCM simulation capabilities to the signal simulator will allow testing of frame synchronizers and decomutation equipment.

Electroporation is the process where externally applied electric fields cause significantly increased permeability of the cell membrane. The increased permeability allows the transport of external compounds into the cell. This is important for applications in electrochemotheropy, electrofusion and drug delivery. Electroporation also has applications in the disinfection of liquids. Given a high enough electric field across the cell membrane, the electroporation process can become irreversible, leading to cell destruction. With the cell membrane under an intense electric field, the cell membrane structure fails causing the cell to die. Conventional liquid beverage disinfection systems rely on slow heating methods requiring large power requirements; this can reduce the taste and quality of some liquids. Pulse generators provide the necessary electric fields to produce the required voltage potential across the cell membrane. The usefulness of electroporation depends on several parameters such as amplitude, frequency and rise/fall times of the electric field. The wave shape also has a bearing on performance, and is limited by the pulse generator topology. A multilevel bipolar waveform is desired with operating frequencies above about 1 kHz. The cascaded H-bridge or full-bridge topology is the most useful as it capable of producing multilevel bipolar waveforms at high frequency. This thesis presents the design and implementation of a multilevel high-voltage pulse generator, capable of creating very high-voltage AC pulses. MOSFET switching devices in conjunction with good layout practices were used to provide required fast switching speeds. The full-bridge topology is used to create a multilevel output profile through cascading of multiple stages. As a full-bridge topology inherently creates a RCL resonant network, there are many challenges associated with mitigating high-frequency noise sources. Two separate stages are built, a low voltage stage capable of outputting up to 200 Vp and a high voltage stage capable of switching up to 1 kVp. A control board was also built for pulse signal generation and user configuration of the output waveforms. The designed pulse generator can produce short pulses of up to 1.4 kVp at frequencies of up to 350 kHz using primarily resistive loads (that simulate a conductive liquid load). Little high frequency switching noise was observable on the output waveform. A single stage pulse generator was also tested with actual liquid loads using an electrode chamber, demonstrating electroporation. The liquid load testing was performed on water and milk derived from milk powder. Results showed that the liquid loads were consistent with primarily resistive loads.

The first topic of this thesis is a voltage boost level clamping circuit for a flash memory which utilizes an implicit feedback loop as well as MOS transistors with different threshold voltages. The proposed design can be added to charge pumps to stabilize the output voltage. The unwanted output voltage spikes introduced by the linear pumping ratio are prevented. Not only are possible damages to memory cores avoided, the power disspation is reduced in contrast with prior regulator methods. The second topic is a switch-current 3-bit CMOS wideband random signal generator, which utilizes a digital normalizer to flatten the distribution of the probability in the entire range of B parameter. The ¡§colored¡¨ random numbers problem in prior designs is resolved. In addition, the coefficients of the proposed design are dynamically adjustable.

This thesis combines Keysight’s SystemVue software with a Vector Signal Analyzer (VSA) and Vector Signal Generator (VSG) to test receiver equalization schemes over physical channels. The testing setup, “Equalization Verification,” is intended to be able to evaluate any equalization scheme over any physical channel, and a decision-directed feed-forward LMS equalizer is used as an example. The decision-directed feed-forward LMS equalizer is shown to decrease the BER from 10-2 to 10-3 (average of all trials) over a CAT7 and CAT6A cable, both simulated and physical, for 1GHz and 2GHz carrier, and 80MHz data rate. A wireless channel, 2.4GHz Dipole Antenna, is also tested to show that the addition of the equalization scheme decreases BER from 10-5 to less than 10-5. Then the simulation and equalization parameters (LMS step size, PRBS, etc.) are changed to further verify the equalization scheme. The simulated channel BER results do not always match the physical channel BER results, but the equalization scheme does decrease BER for both wired and wireless channels. Then transistor-based equalization model is created using both HDL SystemVue components and blocks easily implemented by transistors. The model is then verified using HDL, Spice, and SystemVue simulation. Overall this thesis accomplishes its goal of creating a testing setup, Equalization Verification, to show that adding a given simulated equalization scheme in SystemVue can improve the quality of the link, by decreasing BER by at least an order of magnitude, over a specific physical channel.

Signal generation at high frequency has become increasingly important in numerous wireline and wireless applications. In many gigahertz and millimeter-wave frequency ranges, conventional frequency generation techniques have encountered several design challenges in terms of frequency tuning range, phase noise, and power consumption. Recently, injection locking has been a popular technique to solve these design challenges for frequency generation. However, the narrow locking range of the injection locking techniques limits their use. Furthermore, they suffer from significant reference spur issues. This dissertation presents novel frequency generation techniques based on envelope detection for low-phase-noise signal generation using injection-locked frequency multipliers (ILFMs). Several calibration techniques using envelope detection are introduced to solve conventional problems in injection locking. The proposed topologies are demonstrated with 0.13um CMOS technology for the following injection-locked frequency generators. First, a mixed-mode injection-frequency locked loop (IFLL) is presented for calibrating locking range and phase noise of an injection-locked oscillator (ILO). The IFLL autonomously tracks the injection frequency by processing the AM modulated envelope signal bearing a frequency difference between injection frequency and ILO free-running frequency in digital feedback. Second, a quadrature injection-locked frequency tripler using third-harmonic phase shifters is proposed. Two capacitively-degenerated differential pairs are utilized for quadrature injection signals, thereby increasing injection-locking range and reducing phase error. Next, an injection-locked clock multiplier using an envelope-based frequency tracking loop is presented for a low phase noise signal and low reference spur. In the proposed technique, an envelope detector constantly monitors the VCO's output waveform distortion caused by frequency difference between the VCO frequency and reference frequency. Therefore, the proposed techniques can compensate for frequency variation of the VCO due to PVT variations. Finally, this dissertation presents a subharmonically injection-locked PLL (SILPLL), which is cascaded with a quadrature ILO. The proposed SILPLL adopts an envelope-detection based injection-timing calibration for synchronous reference pulse injection into a VCO. With one of the largest frequency division ratios (N=80) reported so far, the SILPLL can achieve low RMS jitter and reference spur. / Ph. D.

<p>The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.</p>

The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.

The Road Telematics Communicator (RTC) as it is called in Scania. It is the device responsible to keep the vehicle connected and send the vehicle data to the off-board system. It uses data from different sources such as GNSS signals, CAN signal, and wireless Telecom signals. Connected vehicles provide real-time information on positioning, fuel consumption, and vehicle diagnostics. There are acceptance and regression test suites that verify the functionality of RTC. Third-party components such as the GNSS module are not a part of the tests due to technical limitations. Hence RTC lacks automated tests for important features. Due to the lack of complete verification in automated test suites, time-consuming tests must be performed on the road. And trouble reports from the field are difficult to analyze. This thesis provides testing the location accuracy of the GNSS module in vehicles used for telematics applications in the automotive industry, by using a GPS vector signal generator in a controlled lab environment. GNSS consists of GPS, GALILEO, GLONASS, BEIDOU. We are using GPS in this research. The GPS receiver is put under test in a controlled lab environment for testing the Time to First Fix, Location accuracy of GPS receiver, and analyzing the performance with the given inputs. Test cases were created similar to field tests on the signal generator. At this stage, an experiment is performed on the GPS receiver which is connected to the signal generator via RF connector and to a computer via LAN. An input data is sent to the signal generator in the form of SCPI commands. The signal generator processes these commands and generates a signal accordingly. This generated signal is fed to the receiver. With the help of a signal generator, we can generate fields like inputs and verify the behavior of the GPS module. By verifying the behavior of the module, we can develop test cases that show the functionality of the receiver.