This diploma thesis performs a calculation of a steam turbine to drive a feed pump. The research part deals with the basic classification of steam turbines focusing on mechanical drive steam turbines. The second part of the thesis is a controlled extraction pressure optimization for achieving the maximum possible thermic efficiency of the cycle. The last part of the thesis shows a detailed thermodynamic calculation of the mechanical drive turbine along with the basic geometric parameters of the flow canal.

Bidirectional onboard chargers (OBCs) are becoming mainstream commercial charging equipment for electric vehicles (EVs) because of their compactness, flexibility, and demand-response capabilities for power backup. This thesis focuses on the novel phase shift (PS) modulation techniques for efficiency improvement for bidirectional OBCs, including two-stage onboard chargers (TSOBCs) and single-stage onboard chargers (SSOBCs). A comprehensive overview and investigation of the state-of-the-art solutions of bidirectional OBCs are presented. It reviews the current industrial status, industrial applications, and future trends and challenges. A detailed overview of the promising topologies for bidirectional OBCs, including two-stage and single-stage structures, is also discussed in this thesis. Traditional PS modulation has been widely used in the back-end DC/DC converters of the TSOBCs because of its simple implementation. However, it is challenging to keep high efficiency at boundary operating points within wide specifications. Therefore, to improve efficiency at the boundary point for TSOBCs, the hybrid multiple phase shift (HMPS) modulation technique with minimal peak current optimization is presented to maximize the zero-voltage switching (ZVS) range. Compared to traditional single phase shift (SPS) modulation, the experimental results verify that the presented HMPS modulation strategy provides 1%-2% higher efficiency at the boundary points. On the other hand, an improved compact SSOBC topology and novel PS modulation techniques are proposed. Since the traditional PS modulation is challenging for AC/DC converters to keep a unity power factor (PF), novel PS modulation techniques are presented for the proposed SSOBC. Firstly, a sinusoidal single phase shift (SSPS) modulation introduces a sinusoidal phase shift to maintain a high PF and high efficiency within a wide operating point. However, due to the high current at the zero-crossing point of the grid voltage of the SSPS modulation, the novel adaptive sinusoidal single phase shift (ASSPS) modulation is presented to address this issue, which reduces conduction loss and increases efficiency. Secondly, based on the ASSPS modulation, the adaptive sinusoidal extended phase shift (ASEPS) modulation with minimal peak current optimization is presented to introduce one more degree of freedom to extend the ZVS flexibility, which reduces switching loss. Moreover, the minimal peak current optimization reduces transformer current, further decreasing conduction losses. Therefore, the power loss is minimized. Finally, this thesis presents the general design guideline of a 6 kW Silicon Carbide (SiC)-based bidirectional SSOBC, contributing to the further development of bidirectional SSOBC application. Experimental results verify the operating principle and high PF of the proposed SSPS, ASSPS, and ASEPS modulation. 1 kW experimental testing has validated that the peak efficiency is 95.3% with ASSPS modulation and 95.9% with ASEPS modulation. Compared to the existing pulse width modulation (PWM), the ASSPS modulation increased efficiency by 1.1%, and ASEPS modulation further increased by 1.7%. / Thesis / Doctor of Philosophy (PhD)

Isolated inverter can provide galvanic isolation which is necessary for some applications with safety regulations. Traditionally, a two-stage configuration is widely applied with isolated dc-dc stage and a sinusoidal pulse-width-modulated (SPWM) dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Meanwhile, a large dc bus capacitor is needed to attenuate the double line frequency from SPWM for two-stage configuration. Therefore, the single-stage approach including an isolated dc-rectified sine stage and a line frequency unfolder is preferable. Since the unfolder circuit is at line frequency being almost lossless, the isolated dc-rectified sine stage becomes critical. However, the relevant research for the single-stage isolated inverter is limited. People either utilize PWM based converter as dc-rectified sine stage with duty cycle adjustment or apply SRC or LLC resonant converter for better soft switching characteristics. For PWM based converter, hard switching restricts the overall inverter efficiency, while for SRC/LLC, enough wide voltage gain range and full range ZVS are the major issues. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. This dissertation will first propose the optimization methods for LLC converter dc-dc conversion. ZVS models are derived to ensure fully ZVS performance for primary side GaN devices. As a large part in loss breakdown, the optimization for transformer is essential. The LLC converter can achieve above 99% efficiency with proposed optimization approach. Moreover, the channel turn-off energy model is presented for a more accurate loss analysis. With all the design and optimization considerations, a MHz LLC converter based isolated inverter is designed and a hybrid modulation method is proposed, which includes full bridge (FB) VFM for output high line region and half bridge (HB) VFM for output low line region. By changing from FB to HB, the output voltage gain is reduced to half to have a wider voltage gain range. However, the total harmonic distortion (THD) of output voltage at light load will be impacted since the voltage gain will be higher with lighter load at the maximum switching frequency. A MHz LCLCL converter based isolated inverter is proposed for a better output voltage THD at light load conditions. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point at their resonant frequency, which shows superior performance for rectified sine wave generation. Besides the better THD performance, the LCLCL converter based isolated inverter also features for easier control, better ZVS performance and narrower switching frequency range. Meanwhile, the LCLCL based inverter topology has bi-directional power flow capability as well. With variable frequency modulation for ac-dc, this topology is still a single-stage solution compared to the traditional two-stage solution including PFC + LLC configuration. / Doctor of Philosophy / Inverters can convert dc voltage to ac voltage and typically people use two-stage approach with isolated dc-dc stage and dc-ac stage. However, this two-stage configuration suffers from more components count, more complex control and tend to have lower efficiency and lower power density. Therefore, the single-stage solution with dc-rectified sine wave stage and a line frequency unfolder becomes appealing. The unfolder circuit is to unfold the rectifier sine wave to an ac sine wave at the output. Since the unfolder is at line frequency and can be considered lossless, the key design is for the dc-rectified sine stage. The resonant converter featured for soft switching seems to be a good candidate. However, the inverter needs soft switching for the whole range and an enough wide voltage gain, which makes the design difficult, especially the target is high efficiency for the overall inverter. This dissertation aims to provide solutions for a high-efficiency, high-frequency resonant converter based single-stage soft-switching isolated inverter design. The LLC and LCLCL resonant converters are applied as the isolated dc-rectified sine stage with variable frequency modulation (VFM). Therefore, the rectified sine wave generation consists of many dc-dc conversion with different switching frequencies and an efficient dc-rectified sine stage design needs each dc-dc conversion to be with high efficiency. The design considerations and optimization methods for the LLC dc-dc conversion are firstly investigated. Based on these approaches, a MHz LLC converter based isolated inverter is designed with proposed hybrid modulation method. To further improve the light load performance, a MHz LCLCL converter based isolated inverter topology is proposed. The paralleled LC inside the LCLCL resonant tank can naturally create a zero voltage gain point which shows superior characteristics for rectified sine wave generation. Moreover, the LCLCL resonant converter based topology has bi-directional capability as well so it can work well for ac voltage to dc voltage conversion.

Resumo: Este trabalho apresenta um novo conversor PWM monofásico CA-CC, com um único estágio de retificação e correção do fator de potência, utilizando a célula de comutação de três estados. É demonstrado o conversor proposto empregando duas destas células, em substituição as configurações convencionais de duplo estágio, um estágio retificador e outro pré-regulador. A célula de comutação de três estados é composta basicamente por dois interruptores ativos, dois passivos e dois indutores acoplados magneticamente. A topologia desta célula permite que apenas metade da potência de entrada seja processada pelos interruptores ativos, reduzindo assim a corrente de pico sobre estes à metade do valor da corrente de pico da entrada, tornando importante para aplicações em potências mais elevadas. O volume dos elementos reativos (indutores e capacitores) é reduzido, pois, por características topológicas, a freqüência da ondulação da corrente e da tensão é o dobro da freqüência de operação dos interruptores, sendo assim, possível operar o conversor com menores freqüências, diminuindo consequentemente as perdas na comutação. As perdas totais são distribuídas entre todos semicondutores, facilitando a dissipação de calor. O paralelismo dos interruptores é muito atraente para a configuração do circuito estudado, possibilitando o uso de interruptores mais baratos. Outra vantagem é possuir uma menor faixa de operação na região de descontinuidade, ou seja, a faixa de operação no modo de condução contínua é ampliada. É realizado um estudo do conversor boost CC-CC operando com razão cíclica (0 < D < 0,5) e (0,5 < D < 1). Em seguida este conversor é empregado, operando em toda faixa de variação da razão cíclica (0 LÜD LÜ1), no conversor CA-CC de estágio único. O circuito do conversor em questão funciona em malha fechada utilizando o circuito integrado UC3854 para... / Abstract: This work presents a new AC-to-DC PWM single-phase converter, with only one stage including rectification and power factor correction, using the three-state switching cell. It is demonstrated the proposed converter using two of these cells, instead of the conventional configurations that use a rectifier stage and a high-frequency pre-regulator. The three-state switching cell comprises two active switches, two diodes and two coupled inductors. In this topology only part of the input energy is processed by the active switches, reducing the peak current in these switches in a half of the peak value of the input current, making this topology suitable to the operation in larger power levels. The volume of the power reactive elements (inductors and capacitors) is also decreased since the ripple frequency on the output is twice the switching frequency. For a smaller operating frequency, the switching losses are decreased. Due to the topology of the converter, the total losses are distributed among all semiconductors, facilitating the heat dissipation. The parallelism of switches is very attractive for the studied configuration, facilitating the use of cheaper switches. Another advantage of this converter is the smaller region to operate in discontinuous conduction mode or, in other words, the operation range in continuous conduction mode is enlarged. It is developed a study of the DC-to-DC boost converter operating with duty (0 < D < 0,5) and (0,5 < D < 1). Then, this converter was used in full variation range of the duty-cycle (0 < D < 1) in the AC-to-DC single-stage converter. The circuit of this issue converter works with a feedback control line using the integrated circuit UC3854 to do the control in continuous conduction mode for input current with instantaneous average mode. Besides the mathematical analysis and development through... / Orientador: Falcondes José Mendes de Seixas / Coorientador: Grover Victor Torrico Bascopé / Banca: Fabio Toshiaki Wakabayashi / Banca: João Onofre Pereira Pinto / Mestre

abstract: Passive cooling techniques, specifically passive downdraft cooling (PDC), have proven to be a solution that can address issues associated with air conditioning (AC). Globally, over 100 buildings have integrated PDC in its different forms, most of which use direct evaporative cooling. Even though all surveyed buildings were energy efficient and cost-effective and most surveyed buildings were thermally comfortable, application of PDC remains limited. This study aims to advance performance of the single stage passive downdraft evaporative cooling tower (PDECT), and expand its applicability beyond the hot dry conditions where it is typically used, by designing and testing a multi-stage passive and hybrid downdraft cooling tower (PHDCT). Experimental evaluation on half-scale prototypes of these towers was conducted in Tempe, Arizona, during the hot dry and hot humid days of Summer, 2017. Ambient air dry-bulb temperatures ranged between 73.0°F with 82.9 percent coincident relative humidity, and 123.4°F with 7.8 percent coincident relative humidity. Cooling systems in both towers were operated simultaneously to evaluate performance under identical conditions. Results indicated that the hybrid tower outperformed the single stage tower under all ambient conditions and that towers site water consumption was at least 2 times lower than source water required by electric powered AC. Under hot dry conditions, the single stage tower produced average temperature drops of 35°F (5°F higher than what was reported in the literature), average air velocities of 200 fpm, and average cooling capacities of 4 tons. Furthermore, the hybrid tower produced average temperature drops of 45°F (50°F in certain operation modes), average air velocities of 160 fpm, and average cooling capacities exceeding 4 tons. Under hot humid conditions, temperature drops from the single stage tower were limited to the ambient air wet-bulb temperatures whereas drops continued beyond the wet-bulb in the hybrid tower, resulting in 60 percent decline in the former’s cooling capacity while maintaining the capacity of the latter. The outcomes from this study will act as an incentive for designers to consider incorporating PDC into their designs as a viable replacement/supplement to AC; thus, reducing the impact of the built environment on the natural environment. / Dissertation/Thesis / Doctoral Dissertation Architecture 2017

This paper presents the study and development of a topology of nonisolated converter operating at high frequency, which is suitable for the integration of battery banks, photovoltaic panels, and a high voltage dc link in a single conversion stage. The topology is based on the bidirectional version of the three-state switching cell and is recommended for battery charging, while a 200V dc link can be obtained in a single conversion stage using photovoltaic (PV) panels. The presented converter is able to supply a 200V dc link using a battery bank and a PV array and, depending on the solar irradiance level, it is also possible to charge the batteries by using a single conversion stage. Moreover, all the switches of the converter are able to operate under zero voltage switching (ZVS) condition over a wide operation range. The experimental results are obtained from a 500W laboratory prototype, which has been developed and tested in three situations: energy flow from the battery bank to the load, energy flow from the PV panel to the load; and energy flow from the panel to the battery bank, achieving the efficiency of 94,18%, 96,09% e 94,67% respectively. The high gain afforded by this topology and the excellent performance obtained in all operations mode, shows as a solution where the requirement of increasing the voltage to 200V or 400V from low input voltage energy sources, typically 12V, 24V or 48V, provided by batteries, solar panels or others sources of energy, for Uninterruptable Power Supply (UPS), or a DC link, for example. / Este trabalho tem por escopo apresentar o estudo e desenvolvimento de um conversor CC-CC nÃo isolado de trÃs portas, adequado à integraÃÃo em um Ãnico estÃgio de conversÃo: um banco de baterias, um conjunto de painÃis fotovoltaicos e o link CC. A topologia proposta apresenta um conversor boost de alto ganho baseado na versÃo bidirecional da cÃlula de comutaÃÃo de trÃs estados na qual se tem integrado um banco de baterias e um conjunto de painÃis fotovoltaicos com capacidade para gerar um barramento CC de 200V em um Ãnico estÃgio de processamento. A caracterÃstica bidirecional da topologia permite aos painÃis fotovoltaicos carregar as bateiras e alimentar a carga dependendo da incidÃncia solar. No caso de ausÃncia de sol, o banco de baterias supre a carga. Outra importante caracterÃstica deste conversor à a comutaÃÃo suave em modo ZVS para todas as chaves. Foi desenvolvido um protÃtipo experimental com potÃncia nominal de 500W de forma a validar todo o embasamento teÃrico e de simulaÃÃo apresentados. O conversor desenvolvido foi submetido a trÃs condiÃÃes: o fluxo de energia da bateria para a carga, do painel fotovoltaico para a carga e do painel para o banco de baterias, sendo obtido o rendimento de 94,18%, 96,09% e 94,67% respectivamente para cada condiÃÃo. AlÃm disso, as formas de ondas experimentais e de simulaÃÃo para cada condiÃÃo e o comparativo de rendimento de topologias, tambÃm sÃo apresentados. O alto ganho e o rendimento alcanÃado nesta topologia, a torna uma forte soluÃÃo quando hà necessidade de elevar a tensÃo a partir de baterias ou painÃis fotovoltaicos, quando os valores fornecidos por estes geralmente sÃo de 12V, 24V ou 48V. Ressalte-se que este trabalho contribui cientificamente na Ãrea da eletrÃnica de potÃncia, mais especificamente, no que concerne ao estudo e desenvolvimento de novas topologias de conversores CC-CC nÃo isolados de trÃs portas para aplicaÃÃes em energias renovÃveis.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This Master Thesis presents a new analysis, modeling and design guideline for an Insulated Power Factor Corrected Single-Stage Converter. First, the operating principle is presented which provides a better understanding of the converter. So, based on this new analysis, the two operation modes description and the new steady-state gain of the converter are provided. A new control strategy for the input current control-loop is also proposed which provides an improvement of the total harmonic distortion (THD). The conditions to reset the magnetic flux for the high frequency transformer (HFT) into a switching period and the mitigation of the reactive energy are provided. At the sequence, the transfer functions that describe the dynamic behavior of the output voltage and the input current due to perturbations on duty-cycle and input voltage are derived. These dynamic models are derived based on the averaged equivalent circuit (AEC) obtained by modeling an equivalent DC-DC converter. Finally, the design guideline and experimental results for validation of the mathematical analysis and numerical simulation confirmation are provided. / Esta Dissertação de Mestrado apresenta uma nova análise, modelagem e metodologia de projeto de um conversor CA-CC isolado com um único estágio e correção do fator de potência. Inicialmente, é apresentado o princípio de operação do conversor em estudo propiciando um melhor entendimento do funcionamento do mesmo. Assim, baseada na nova análise, são apresentados os dois modos de operação do conversor e o novo ganho estático resultante. Também é proposta uma nova estratégia de controle para a corrente de entrada do conversor proporcionando uma redução na distorção harmônica total (DHT). Também serão estabelecidas as condições necessárias para a desmagnetização do núcleo do transformador de alta freqüência (TAF) em um período de chaveamento e a minimização de reativos circulantes. Posteriormente, são obtidas as funções de transferências que descrevem o comportamento dinâmico da tensão de saída e da corrente de entrada para perturbações na variável de controle ou na tensão de entrada. Esses modelos dinâmicos serão derivados do circuito médio equivalente (CME) obtido através da modelagem do conversor em estudo operando como um conversor CC-CC equivalente. Por fim, são apresentadas uma metodologia de projeto e os resultados experimentais para a validação da análise matemática e confirmação dos resultados obtidos através de simulações numéricas.

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.

Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.