It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects. Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more. To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycle's resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results. Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop. This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phase's off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a "fast" controller, the current sampling and DPWM might introduce some delay to the loop. After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller. With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification. / Master of Science

In this thesis, a detailed study of the electrical and optical characterisations of Heterojuction Bipolar Transistors (HBTs) for optical detection is presented. By comparing both DC and optical characterisations between In0.49Ga0.51P/GaAs Single Heterojuction Bipolar Transistors (SHBTs) and Double Heterojuction Bipolar Transistors (DHBTs), the advantages of using the DHBT as a short wavelength detector are shown. Phenomena related to the base region energy band bending in the DHBT caused by a self-induced effective electric field is discussed and its effects on the performance of the device are elaborated. The use of an eye diagram has been employed to provide requisite information for performance qualification of SHBT/DHBT devices. These give a more detailed understanding compared to conventional S-parameters method. A detailed comparison of In0.49Ga0.51P/GaAs SHBT and DHBT performance using an eye diagram as a functional tool by adopting a modified T-shaped small signal equivalent circuit are given. By adopting this modified T-shaped small signal equivalent circuit, the use of In0.49Ga0.51P/GaAs Double Heterojuction Phototransistors (DHPT) as a short wavelength photodetector is analysed. It is therefore shown that an eye diagram can act as a powerful tool in HBTs/HPTs design optimisations, for the first time in this work. In order to predict the spectral response (SR) and optical characterisations of GaAs-based HPTs, a detailed theoretical absorption model is also presented. The layer dependence of an optical flux absorption profile, along with doping dependent absorption coefficients are taken into account for the optical characterisation prediction. With the aim of eliminating the limitation of current gain as a prerequisite, analytical modelling of SR has been developed by resolving the continuity equation and applying realistic boundary conditions. Then, related physical parameters and a layer structure profile are used to implement simulations. A good agreement with the measured results of the Al0.3Ga0.7As/GaAs HPT is shown validating the proposed theoretical model.

Motivated by the recent commercialization of gallium-nitride (GaN) switches, an effort was initiated to determine whether it was feasible to switch the flyback converter at 5 MHz in order to improve the power density of this versatile isolated topology. Soft switching techniques have to be utilized to eliminate the switching loss to maintain high efficiency at multi-megahertz. Compared to the traditional modeling of zero-voltage-switching quasi-square-wave converters, a numerical methodology of parameters design is proposed based on the steady-state model of zero-voltage switching quasi-square-wave flyback converter. The magnetizing inductance is selected to guarantee zero-voltage switching for the entire input and load range with the trade-off design for conduction loss and turn-off loss. A design methodology is introduced to select a minimum core volume for an inductor or coupled inductors experiencing appreciable core loss. The geometric constant Kgac = MLT/(Ac2WA) is shown to be a power function of the core volume Ve, where Ac is the effective core area, WA is the area of the winding window, and MLT is the mean length per turn for commercial toroidal, ER, and PQ cores, permitting the total loss to be expressed as a direct function of the core volume. The inductor is designed to meet specific loss or thermal constraints. An iterative procedure is described in which two- or three-dimensional proximity effects are first neglected and then subsequently incorporated via finite-element simulation. Interleaved and non-interleaved planar PCB winding structures were also evaluated to minimize leakage inductance, self-capacitance and winding loss. The analysis on the trade-off between magnetic size, frequency, loss and temperature indicated the potential for a higher density flyback converter. A small-signal equivalent circuit of QSW converter was proposed to design the control loop and to understand the small-signal behavior. By adding a simple damping resistor on the traditional small-signal CCM model, it can predict the pole splitting phenomenon observed in QSW converter. With the analytical expressions of the transfer functions of QSW converters, the impact of key parameters including magnetizing inductance, dead time, input voltage and output power on the small-signal behavior can be analyzed. The closed-loop bandwidth can be pushed much higher with this modified model, and the transient performance is significantly improved. With the traditional fix dead-time control, a large amount of loss during dead time occurred, especially for the eGaN FETs with high reverse voltage drop. An adaptive dead time control scheme was implemented with simple combinational logic circuitries to adjust the turn on time of the power switches. A variable deadtime control was proposed to further improve the performance of adaptive dead-time control with simplified sensing circuit, and the extra conduction loss caused by propagation delay in adaptive dead-time control can be minimized at multi-megahertz frequency. / Ph. D. / With the fast development of telecom, computer and network systems, high efficient and small volume power supplies are highly desired. A typical method for achieving high power density involves increasing the frequency and implement soft-switching techniques to minimize loss. Thanks to the recent commercialization of the advanced semiconductor gallium-nitride (GaN) switches, it is feasible to design high density power supplies and cost effective power system. Several challenges including optimization of power converter, high frequency magnetics and implementation of control architecture have been addressed in this dissertation which helps to realize this compact power system. With the implementation of proposed circuit model and seminumerical design procedures for magnetics, a 30W high-frequency isolated DC/DC converter with planar inductor is fabricated to verify the theoretical analysis, which also demonstrates much improved performances.

No description available.

The unconventional improvements in the power electronics field have been the primary reason for massive deployment of renewable energy sources in the electrical power grid over the past several decades. This needed trend, together with the increasing penetration of micro-, and nano- grids, is bringing significant improvements in system controllability, performance, and energy availability, but is fundamentally changing the nature of electronically-interfaced sources and loads, altering their conventionally mild aggregate dynamics, and inflicting low- and high- frequency dynamic interactions that never before existed at this magnitude. This problem is not restricted only to the grid; modern electronic power distribution systems built for airplanes, ships, electric vehicles, data-centers, and homes, comprise dozens, even hundreds of power electronics converters, produced by different manufacturers, who provide very limited details on converters' dynamic behavior - distinctiveness that has the highest impact on how two converters, or converter and a system interact. Consequently, substantial dispersion of power electronics into the future grid will significantly depend on engineers' capability to understand how to model and dynamically control power flow and subsystem interactions. It is therefore essential to continue developing innovative methods that allow easier system-level modeling, continuous monitoring of dynamic interactions, and advanced control concepts of power electronics converters and systems. The dissertation will start with a "black box" approach to modeling of three-phase power electronics converters, introducing a method to remove source and load dynamics from in-situ measured terminated frequency responses. It will be then shown how converter, itself, can perform an online stability assessment knowing its own unterminated dynamics, and being able to measure all terminal immittances. The dissertation will further advance into an approach to control power electronics converters based on the electro-mechanical duality with synchronous machines, and end with selected examples of system-level operation, where small-signal instability in multi-source power systems can be mitigated using this concept. / Ph. D. / The modern technological advancements and ever-increasing needs for a sustainable future silently demand a serious revision of the conventional practice in electricity production, distribution, and utilization. These technologies are already challenging the limits of the biggest and most complex system ever built by humankind - the electrical grid. One practical solution to this problem is much higher dispersion of electronic power conversion systems capable of decoupling dynamics between system sources, distribution, and loads, while improving system controllability, reliability, and efficiency. Such a trend is already happening, and there has been an increased immersion of power electronics converters in electric cars, ships, airplanes, and the grid, in an effort to replace their traditional thermal, mechanical, hydraulic, and pneumatic systems. The goals have been to reduce the size, weight, and operational costs while increasing efficiency and reliability. In all these applications, a majority of energy sources and loads are interfaced to the power system through power electronics converters ranging in power from few watts to hundreds of megawatts. However, massive dispersion of power electronics into the future grid will significantly depend on engineers’ capability to understand how to model and dynamically control power flow and subsystem interactions. It is important to continue researching innovative methods that allow easier system-level modeling, continuous monitoring of interactions, and advanced control concepts of power electronics converters and systems. This dissertation hence addresses modeling of power electronics converters using their behavioral models, and shows how these models can assist the stability assessment of the system converters operate in. Additionally, dissertation presents an alternative way to control power electronics converters to behave as synchronous machines, and how this concept can be used to mitigate some stability problems.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This Master Thesis presents the development of a new dynamic model for the DC-DC Zero-Voltage-Switching Phase-Shift-Modulated Full-Bridge (ZVS-PSM-FB).At first, the ZVSPSM-FB converter is analyzed and the Steady-State equations are derived. Then, using the ac equivalent circuit modeling technique, it is derived two new ZVS-PSM-FB dynamical models, based on step operation of the converter and steady-state converter equations. These two new ZVS-PSM-FB dynamical models with two dynamical models previously presented in the literature are used to perform a frequency response and a transfer-function DC-gain comparison to verify the performance of the dynamical models. Comparison results shows that our second model here derived presents a better performance among other models, keeping the desirable characteristics as simple polynomial ratio transfer-functions, excellent theoretical accuracy of transfer-functions DC-gains, transfer-functions coefficients independency of circuit parasitics components, excepting the primary leakage inductance. Even in this work, it is shown frequency response experimental results of the ZVS-PSM-FB converter, designed following telecommunications rectifiers power supplies standards. / Esta Dissertação de Mestrado apresenta o desenvolvimento de um novo modelo dinâmico para o conversor CC-CC Ponte-Completa Modulado por Deslocamento de Fase e com Comutação em Zero de Tensão (ZVS-PSM-FB). Inicialmente, o conversor ZVS-PSM-FB é analisado, onde são derivadas as equações que definem a operação em regime-permanente do conversor. A seguir, utilizando-se da técnica de modelagem ca média de conversores estáticos, deriva-se dois novos modelos dinâmicos para o conversor, tendo por base as etapas de operação do conversor e as equações de regime-permanente. Feito isso, os dois modelos aqui derivados, são comparados com outros dois modelos dinâmicos já apresentados na literatura para verificar seus desempenhos quanto à resposta em freqüência e resposta do ganho-cc das funções de transferências à variações de carga do conversor, dos modelos dinâmicos. Resultados desta comparação mostram que o segundo modelo aqui derivado é o que apresenta melhor desempenho entre os modelos comparados, mantendo características desejáveis de simples formato de função de transferência como razão de polinômios, precisão teórica excelente para resposta de ganho-cc das funções de transferências e não-dependência dos coeficientes das funções de transferências de parâmetros parasitas do circuito, a menos da indutância de dispersão do transformador. Ainda neste trabalho, são mostrados resultados experimentais da resposta em freqüência do conversor ZVS-PSM-FB, projetado com especificações de normas para retificadores chaveados de alta-freqüência para equipamentos de telecomunicações.

Les études qui seront présentées dans le cadre de cette thèse portent sur le développement et l’optimisation des techniques pour la modélisation compacte des transistors bipolaires à hétérojonction (TBH). Ce type de modélisation est à la base du développement des bibliothèques de composants qu’utilisent les concepteurs lors de la phase de simulation des circuits intégrés. Le but d’une technologie BiCMOS est de pouvoir combiner deux procédés technologiques différents sur une seule et même puce. En plus de limiter le nombre de composants externes, cela permet également une meilleure gestion de la consommation dans les différents blocs digitaux, analogiques et RF. Les applications dites rapides peuvent ainsi profiter du meilleur des composants bipolaires et des transistors CMOS. Le défi est d’autant plus critique dans le cas des applications analogiques/RF puisqu’il est nécessaire de diminuer la puissance consommée tout en maintenant des fréquences de fonctionnement des transistors très élevées. Disposer de modèles compacts précis des transistors utilisés est donc primordial lors de la conception des circuits utilisés pour les applications analogiques et mixtes. Cette précision implique une étude sur un large domaine de tensions d’utilisation et de températures de fonctionnement. De plus, en allant vers des nœuds technologiques de plus en plus avancés, des nouveaux effets physiques se manifestent et doivent être pris en compte dans les équations du modèle. Les règles d’échelle des technologies plus matures doivent ainsi être réexaminées en se basant sur la physique du dispositif. Cette thèse a pour but d’évaluer la faisabilité d’une offre de modèle compact dédiée à la technologie avancée SiGe TBH de chez ST Microelectronics. Le modèle du transistor bipolaire SiGe TBH est présenté en se basant sur le modèle compact récent HICUMversion L2.3x. Grâce aux lois d’échelle introduites et basées sur le dessin même des dimensions du transistor, une simulation précise du comportement électrique et thermique a pu être démontrée.Ceci a été rendu possible grâce à l’utilisation et à l’amélioration des routines et méthodes d’extraction des paramètres du modèle. C’est particulièrement le cas pour la détermination des éléments parasites extrinsèques (résistances et capacités) ainsi que celle du transistor intrinsèque. Finalement, les différentes étapes d’extraction et les méthodes sont présentées, et ont été vérifiées par l’extraction de bibliothèques SPICE sur le TBH NPN Haute-Vitesse de la technologie BiCMOS avancée du noeud 55nm, avec des fréquences de fonctionnement atteignant 320/370GHz de fT = fmax. / The aim of BiCMOS technology is to combine two different process technologies intoa single chip, reducing the number of external components and optimizing power consumptionfor RF, analog and digital parts in one single package. Given the respectivestrengths of HBT and CMOS devices, especially high speed applications benefit fromadvanced BiCMOS processes, that integrate two different technologies.For analog mixed-signal RF and microwave circuitry, the push towards lower powerand higher speed imposes requirements and presents challenges not faced by digitalcircuit designs. Accurate compact device models, predicting device behaviour undera variety of bias as well as ambient temperatures, are crucial for the development oflarge scale circuits and create advanced designs with first-pass success.As technology advances, these models have to cover an increasing number of physicaleffects and model equations have to be continuously re-evaluated and adapted. Likewiseprocess scaling has to be verified and reflected by scaling laws, which are closelyrelated to device physics.This thesis examines the suitability of the model formulation for applicability to production-ready SiGe HBT processes. A derivation of the most recent model formulationimplemented in HICUM version L2.3x, is followed by simulation studies, whichconfirm their agreement with electrical characteristics of high-speed devices. Thefundamental geometry scaling laws, as implemented in the custom-developed modellibrary, are described in detail with a strong link to the specific device architecture.In order to correctly determine the respective model parameters, newly developed andexisting extraction routines have been exercised with recent HBT technology generationsand benchmarked by means of numerical device simulation, where applicable.Especially the extraction of extrinsic elements such as series resistances and parasiticcapacitances were improved along with the substrate network.The extraction steps and methods required to obtain a fully scalable model library wereexercised and presented using measured data from a recent industry-leading 55nmSiGe BiCMOS process, reaching switching speeds in excess of 300GHz. Finally theextracted model card was verified for the respective technology.