Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today¡¦s ESL can verify the whole system simulation include the Processor, Bus, Memory¡K such as the HWs. It also can run a small program on the system. But it is hard to verify the larger program - such as the operation system because the limitations of the simulation speed. Currently some people proposed the QEMU-SystemC virtual platform. It can greatly speed up the CPU simulation speed. But the abstract simulated CPU has no timing information. It is infeasible to explore the system execution time and performance. We proposed the method: CPU, Cache, TLB and SDRAM with timing model; connect the CPU and the designed HW in TLM bus module in the HW/SW co-simulation. We can analyze the performance in the estimated timing information, and it will not take many simulation times. In addition, we developed the analysis program to show the execution time in each program block. It can help designer to locate the performance bottleneck quickly in the complex HW/SW. A case study is the 3D graphic SoC. We find the performance bottleneck in HW/SW design according the performance information purposed by our work.

In the last years, with more and more transistors can fit into a chip, the growth the IC design complexity is fast and original design flow can¡¦t cater for designers. Therefore, so many people promote to integrate the system into a single chip gradually with the last technology using the concept of hardware/software co-design. In this thesis, we use the hardware/software co-design concept to build a simple video codec from system level and implement it on the ARM¡¦s SOC platform. We focus on the hardware/software co-ordination. Because we use the platform-based design method, the build hardware/software modules can be used in the similar architecture on the ARM platform In our Video codec system, discrete wavelet transform(DWT) and RGBtoYCbCr are the most timing-consuming parts. Since DWT has inherent scalability and excellent features of energy compaction, it has been applied widely in the various image compression systems. We adopt the 5-3 filter lifting-based DWT in the hardware part of our system and design three different lifting-based DWT architectures by using the high level synthesis concept to optimize the hardware utilization and speed. In the premise of not increasing memory access times and additional processes of software, we overcome the boundary extension of DWT and verify it by means of FPGA after combining it with the RGBtoYCbCr hardware architecture. Finally, the hardware part is integrated with the other part implemented by software, we build a completely video encode system on the ARM SOC platform using the hardware/software co-design.

Operating batteries in parallel is attempted to overcome the problems with conventionally used battery bank, in which batteries are connected in series. The problems and the management with the operation of serial connected batteries are first addressed. The related topics to the parallel configuration are reviewed. Then, the parallel configuration with battery power modules is proposed. The battery power module can be realized with different dc-to-dc converters for different applications. When batteries are charged in parallel, the problem of over-charge can be avoided. With parallel operation, the discharging currents of the batteries are independently controlled but are coordinated to execute a full amount load current. This allows for scheduling the discharging profiles under different operating conditions. As a result, a sophisticated discharging profile can be realized to utilize the available stored energy in batteries. On the other hand, some of the batteries may take rest or be isolated from the system for the detections at a time. This facilitates the estimations of the state of charge (SOC) and the state of health (SOH). Moreover, the completely exhausted or damaged batteries can be isolated from the battery power supply bank without interrupting the system operation. Experiments are carried out on battery power modules with lead-acid batteries incorporating with associated buck-boost converters. The experimental results demonstrate that a more efficient utilization of battery energy can be achieved. On the other hand, a more reasonable management can be done with simple estimation methods of the SOC and the SOH.

For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-¢º processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.

Europeanization has been the subject of various studies in the last decades. It has been operationalized as a historical process, as a cultural diffusion of European values, as a process of institutional adaptation of institutions and lastly as the adaptation of policies. Taking the last approach, this thesis aims to examine the nature and the extent of the impact of the European Union&rsquo / s poverty and social exclusion strategy on Turkish poverty and social exclusion regime in the EU accession process. It takes up a bottom-up research design by employing the domestic change as the dependent and the possible impact of the EU as the independent variable and questions whether and to what extent the EU accession process has an impact on the degree, nature and direction of domestic change in the field of poverty and social exclusion in Turkey in the last decade. It concludes that there has been a change in poverty and social exclusion policies in the last decade to varying degrees with respect to objectives, principles, procedures and instruments / however, the impact of the EU has been limited to policy learning.

Continuous improvements in semiconductor fabrication density are enabling new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processing with high-density memory. Such architectures are generally called Processor-in-Memory or Intelligent Memory and can support high-performance computing by reducing the performance gap between the processor and the memory. This architecture combines various processors in a single system. These processors are characterized by their computational and memory-access capabilities in performance and energy consumption. Two main problems addressed here are how to improve the performance and reduce the energy consumption of applications running on Processor-in-Memory architectures. Accordingly, a novel strategy must be developed to identify the capabilities of the different processors and dispatch the most appropriate jobs to them to exploit them fully. Accordingly, this study proposes a novel automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of Processor-in-Memory architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analytical approaches. The strategy of the SAGE system, which decomposes the original program into blocks and produces a feasible execution schedule for the host and memory processors, is also investigated. Hence, several techniques including statement splitting, weight evaluation, performance scheduling and energy reduction scheduling are designed and integrated into the SAGE system to automatically transform Fortran source programs to improve the performance of the program or reduce energy consumed by the program executed on Processor-in-Memory architecture. This thesis provides detailed techniques and discusses the experimental results of real benchmarks which are transformed by SAGE system and targeted on the Processor-in-Memory architecture.

This thesis proposes an enhanced ampere-hour counting method based on the depth-of-discharge (DOD) to estimate the state-of-charge (SOC) and state-of-health (SOH) for lead-acid batteries. Not only the losses at different discharging currents, but also the releasable capacity at the exhausted state caused by the larger discharging current are considered and compensated. Furthermore, the SOH is revaluated at the exhausted state by the maximum releasable capacity, consequently leading to more accurate SOC estimation. Through the experiments that emulate practical operations, the experimental results reveal that the maximum error is less than 6 %.

A novel battery power system configured by the battery power modules (BPMs) is proposed. Each BPM consists of a single battery pack or a battery bank equipped with an associated DC/DC converter. The output ports of BPMs can be connected in series for the high voltage applications, or in parallel to cope with a higher power or energy. For a large scale battery power system, a number of BPMs can be arrayed with combination of series and parallel connections to meet the load requirements. These all configurations allow the BPMs be operated individually. Consequently, the discharging currents of the batteries can be independently controlled, but coordinated to provide a full amount of the load current. The performances of BPMs connected in both parallel and series at outputs are analyzed theoretically and discussed from the experimental results. Batteries operating independently do not suffer from charge imbalance, and thus can avoid being over-charged or over-discharged, so that the life cycle can be prolonged. Furthermore, sophisticated discharging profiles such as intermittent currents can be realized to equalize the charges and thus to efficiently utilize the available stored energy in batteries. During the operation period, some of the batteries may take rest or be isolated from the system for the open-circuit measurement, facilitating the estimation of the state-of-charge (SOC) and the evaluation of the state-of-health (SOH). With the benefit of independent operation, the BPMs can be discharged with a scheduled current profile, such as intermittent discharging. The investigation results show that the average current plays the most important role in current discharging. By detecting the battery voltage at the break time, an SOC estimation method based on the dynamically changed open-circuit voltage exhibits an acceptable accuracy in a shorter time with considerations of the previous charging/discharging currents and the depth-of- discharge (DOD). In addition, the coulomb counting method can be enhanced by evaluating the SOH at the exhausted and fully charged states, which can be intended on the independently operated BPMs. Through the experiments that emulate practical operations, the SOC estimation methods are verified on lead-acid batteries and lithium-ion batteries to demonstrate the effectiveness and accuracy.

<p>The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.</p><p>As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers.</p><p>As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again.</p><p>The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed.</p><p>To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.</p>

<p>The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process.</p><p>An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug.</p><p>Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation.</p><p>This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test.</p><p>Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored.</p><p>The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.</p>