Com o mercado dos dispositivos móveis em expansão, a necessidade de desenvolver tecnologias que atendam a demanda por energia se intensi cou. Geralmente, estes dispositivos móveis são alimentados por uma bateria que deve ser recarregada a cada intervalo de tempo. Por esta razão, é importante conhecer o tempo que a bateria mantém o dispositivo operacional, isto é, seu tempo de vida. Um dos métodos para realizar a predição do tempo de vida de baterias de dispositivos móveis é a utilização de modelos matemá- ticos, que simulam o processo de descarga de energia das baterias. Entre os modelos mais referenciados na literatura técnica, destacam-se os modelos eletroquímicos, os modelos de circuitos elétricos, os modelos estocásticos, os modelos analíticos, os modelos via teoria de Identi cação de Sistemas e os modelos híbridos. Os modelos híbridos são vantajosos, pois permitem a união de dois ou mais modelos de características distintas. Inserido nessa categoria, este trabalho tem por objetivo propor a modelagem matemática do tempo de vida de baterias de Lítio Íon Polímero (Li-Po), através do desenvolvimento de um modelo híbrido baseado na união do modelo elétrico para Predizer Runtime e Características V-I de uma bateria e do modelo analítico Lei de Peukert Estendida. O modelo é implementado computacionalmente na ferramenta computacional MatLab. Os dados experimentais são obtidos de uma plataforma de testes que simula o descarregamento de baterias, considerando baterias do tipo Li-Po. A validação ocorre a partir da comparação das simulações realizadas, com os dados da plataforma, utilizando per s de descarga constantes e variáveis. Por m, é realizada a comparação do modelo obtido com outros modelos na literatura. Os resultados das simulações comprovam que o modelo hí- brido proposto é mais simples e computacionalmente exível, quando comparado a outros modelos híbridos, além de apresentar resultados satisfatórios para a predição do tempo de vida de baterias. / 94 f.

As the demands of communication systems have become more complex and varied, software defined radios (SDR) have become increasingly popular. With behavior that can be modified in software, SDR's provide a highly flexible and configurable development environment. Despite its programmable behavior, the maximum performance of an SDR is still rooted in its hardware. This limitation and the desire for the use of SDRs in different applications have led to the rise of various pieces of hardware to serve as SDR platforms. These platforms vary in aspects such as their performance limitations, implementation details, and cost. In this way the choice of SDR platform is not solely based on the cost of the hardware and should be closely examined before making a final decision. This thesis examines the various SDR platform families available on the market today and compares the advantages and disadvantages present for each during development. As many different types of hardware can be considered an option to successfully implement an SDR, this thesis specifically focuses on general purpose processors, system on chip, and field-programmable gate array implementations. When examining these SDR families, the Freescale BSC9131 is chosen to represent the system on chip implementation, while the Nutaq PicoSDR 2x2 Embedded with Virtex6 SX315 is used for the remaining two options. In order to test each of these platforms, a Viterbi algorithm is implemented on each and the performance measured. This performance measurement considers both how quickly the platform is able to perform the decoding, as well as its bit error rate performance in order to ascertain the implementations' accuracy. Other factors considered when comparing each platform are its flexibility and the amount of options available for development. After testing, the details of each implementation are discussed and guidelines for choosing a platform are suggested.

Nesse trabalho é apresentada uma arquitetura que habilita a geração de MPSoCs (Multiprocessors Systems-on-Chip) heterogêneos escaláveis, baseados em barramento, suportando ainda o uso de diferentes organizações de memória. A comunicação entre as tarefas é especificada por meio de uma estrutura de memória compartilhada, que evita colisões e promove ganhos energéticos através do disparo dinâmico de clock gating. Também é introduzida a técnica DCF (Dynamic Core Freezing), que incrementa a eficiência energética do MPSoC tirando proveito dos ciclos ociosos dos processadores durante os acessos à memória. Mais, a combinação das organizações de memória propostas habilita a exploração de migração de tarefas na arquitetura proposta, por meio da troca de contexto das tarefas na memória compartilhada. Além disso, é mostrado o simulador de alto-nível, baseado na arquitetura proposta, criado com o propósito de extrair os ganhos energéticos propiciados com o uso do clock gating e da técnica DCF. O simulador aceita como entrada arquivos de trace de execução de aplicações Java, com os quais ele gera um novo arquivo contendo o mapeamento das instruções encontradas nos arquivos de trace para diferentes classes de instrução. Dessa forma, podem ser modeladas diferentes arquiteturas de processadores, usando o arquivo com o mapeamento para simular o MPSoC. Mais, o simulador habilita ainda a exploração das diferentes organizações de memória da arquitetura proposta, de maneira que se pode estimar o seu impacto no número de instruções executadas, contenções no barramento, e consumo energético. Experimentos baseados em uma aplicação sintética, executando em um MPSoC composto por diferentes versões de um processador Java mostram um grande aumento na eficiência energética com um custo mínimo em área. Além disso, também são apresentados experimentos baseados em aplicações do benchmark SPECjvm98, que mostram o impacto causado na eficiência energética quando o tipo de aplicação é alterado. Mais, os experimentos mostram drásticos ganhos energéticos obtidos com a aplicação da técnica DCF sobre as memórias do MPSoC. / In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of Java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a Java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a Java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF technique to the MPSoC memories.

O objetivo deste trabalho é propor técnicas de alocação dinâmica de tarefas periódicas em MPSoCs homogêneos, com processadores interligados por uma rede emchip do tipo malha, visando redução do consumo de energia do sistema. O foco principal é a definição de uma heurística de alocação, não se considerando protocolos de escalonamento distribuído, uma vez que este ainda é um primeiro estudo para o desenvolvimento de um alocador dinâmico. Na arquitetura alvo utilizada, cada nodo do sistema é dado como autônomo, possuindo seu próprio escalonador EDF. Além disso, são aplicadas técnicas de voltage scaling e power managmenent para redução do consumo de energia durante o escalonamento. Durante a pesquisa do estado da arte, não foram encontradas técnicas de alocação dinâmica em NoCs com restrições temporais e minimização do consumo de energia. Por isso, esse trabalho se concentra em avaliar técnicas de alocação convencionais, como bin-packing e técnicas baseadas em teoria de grafos, no contexto de sistemas embarcados. Dessa forma, o modelo de estimativas do consumo de energia de alocações é baseado no escalonamento de grafos de tarefas, e foi utilizado para implementar a ferramenta Serpens com este propósito. Os grafos de tarefas utilizados nos experimentos são tirados do benchmark E3S – Embedded System Synthesis Benchmark Suite, composto por um conjunto de grafos de tarefas gerados aleatoriamente com a ferramenta TGFF – Task Graph for Free, a partir de dados de aplicações comuns em sistemas embarcados obtidos no EEMBC – Embedded Microprocessor Benchmark Consortium. Entre as heurísticas de bin-packing, Best-Fit, First-Fit e Next-Fit geram alocações com concentração de carga, enquanto a heurística Worst-Fit faz balanceamento de carga. O balanceamento de carga favorece a aplicação de voltage scaling enquanto a concentração favorece o power management. Como o bin-packing não contempla comunicação e dependência entre tarefas em seu modelo, o mesmo foi reformulado para atender esta necessidade. Nos experimentos, a alocação inicial com bin-packing original apresentou perdas de deadlines de até 84 % para a heurística Worst-Fit, passando para perdas em torno de 16% na alocação final, praticamente com o mesmo consumo de energia, após a reformulação do modelo. / The goal of this work is to offer dynamic allocation techniques of periodic tasks in mesh networks-on-chip, aiming to reduce the system power consumption. The main focus is the definition of an allocation heuristic, which does not consider distributed scheduling protocols, since this is the beginning of a study for the development of a dynamic partitioning tool. In the target architecture, each system node is self-contained, that is, the nodes contain their own EDF scheduler. Besides, voltage-scaling and power management techniques are applied for reducing power consumption during the scheduling. To the best of our knowledge, this is the first research effort considering both temporal constraints and power consumption minimization on the dynamic allocation of tasks in a mesh NoC. This way, our concentrates in the evaluation of dynamic allocation techniques, which are generally used in distributed systems, in the embedded systems context, as bin-packing and graph theory based techniques. Therefore, the estimation model for power consumption is based on task graph scheduling, and it was used for implementing the Serpens tool with this purpose. The task graphs used in the experiments were obtained from the E3S benchmark (Embedded System Synthesis Benchmark Suite), which is composed by a set of task graphs randomly generated with the TGFF tool (Task Graph for Free), from common application data obtained from the EEMBC (Embedded Microprocessor Benchmark Consortium). Among the bin-packing heuristics, Best-Fit, First-Fit, and Next-Fit generate allocations with load concentration, while the Worst-Fit heuristics works with load balancing. Load balancing favors the application of voltage scaling, while load concentration favors the utilization of power management. Since the bin-packing model does not consider inter-task communication and dependency, it has been modified to fulfill this need. In the experiments, the initial allocation using the original bin-packing model presented deadline losses of up to 84% for the Worst-Fit heuristic, changing for losses around 16% in the final allocation, after modification of the model, maintaining almost the same power consumption.

On présente le réseau CYCLADES, les options prises par les concepteurs et on décrit les différents niveaux de protocoles, en particulier la station de transport. On décrit les différentes methodes pour implanter la station de transport d'un ordinateur hôte. On propose une décomposition des fonctions de la station de transport en deux parties : une externe et une résiduelle. On présente sommairement les différents types d'architecture à plusieurs microprocesseurs. On décrit les choix et options prises dans la conception du système PIAR. On décrit l'architecture logicielle et matérielle du système PIAR ainsi que les moyens de communication et synchronisation.

<p>The purpose of this study is to look into how detained swedish juveniles, in the ages between 15 an 20, experience time in custody. The primary questions are; To what exctent do juveniles understand their situation? To what exctent can juveniles handle their situation? Do the juveniles find meaning in their situation and if so, what aspects of the detention is considered meaningful? The study is based on seven qualitative interviews with young men detained at a youth custody ward at Kronobergshäktet in Stockholm. The theory used to analyze the interview results is Antonovskys theory of sence of coherence (SOC). A salient feature in the young mens experiences was that all of them had the ability to regard some of the aspects of the detention as meaningful. These positive aspects includes time for reflection and a possibility to break destructive patterns. Further more, it was evident that most of the respondents experienced that their lives contained elements of importance, such as family, education and future goals. Nevertheless, isolation, lack of contact with family and friends, powerlessness and worries about the future, were aspects of the detention that had a negative influence on all of the respondents in variyng degrees.</p>

<p>Syftet med vår studie var att undersöka på vilket sätt ideellt arbete upplevs av arbetslösa personer. Vi valde att göra studien på den ideella musikföreningen Pipeline. En kvalitativ metod användes för att kunna ta del av intervjupersonernas upplevelser gällande ideellt arbete. Studien bestod av fem intervjuer med personer som hade eller haft praktik på Pipeline. Praktiken var arbetspraktik för arbetslösa eller praktik för ungdomar på individuella programmet. Resultatet visade att personerna upplevde gemenskap, bra ledarskap, motivation och en känsla av sammanhang i det ideella arbetet.</p> / <p>The purpose of our study was to see in which way unemployed person´s life was affected by working in a voluntary organization. The study was made on the music organization Pipeline. We choose to make the study in a quality method, to be able to take part in the people´s own experiences with voluntary work. The study was made by interviewing five persons who had work related practice for unemployed or for youths at the individual program. The results showed that the people experienced fellowship, good leadership, motivation, a sense of coherence in voluntary work.</p>

<p>Att ha möjlighet till återhämtning är viktigt för hälsan. I denna studie är det återhämtning från arbetet efter arbetstidens slut som står i fokus, det vill säga den som företrädesvis sker på fritiden. Med fritid avser jag i denna intervjustudie den tid vi inte ägnar åt lönearbete. Fritidsintressen, föreningsliv, olika engagemang är aktiviteter som konkurrerar om vår tid. Det kan ibland vara ren återhämtning men ibland åtaganden som ökar stressen. Om utrymmet för återhämtning är ringa eller inte existerar finns en ökad risk för bland annat stressrelaterade besvär. Faktorer som är avgörande för vår återhämtning och fritid finns på individnivå, i vårt arbete, i vår psykosociala miljö och på samhällsnivå. Dagens folkhälsopolitik fokuserar på bestämningsfaktorer vilket är "faktorer i samhällsorganisationen och människors livsvillkor och levnadsvanor som bidrar till hälsa eller ohälsa". Människor verkar inom olika ramar, har olika resurser och reagerar olika på stressorer vi ställs inför. Enligt Aaron Antonovskys så har individer olika motståndskraft, vissa förblir friska, klarar sig bra trots stora påfrestningar vilket hänger samman hur de hanterar sina motgångar och sin förmåga att göra tillvaron sammanhängande (KASAM, Känsla Av SAMmanhang).</p><p>Syftet har varit att undersöka hur (dubbel)arbetande kvinnor upplever och skapar sina återhämtningsmöjligheter på fritiden. Vidare för att belysa och skapa reflektion kring situationer som, kanske till stor del i det dolda kan ge ohälsosamma effekter. Undersökningen genomfördes med hjälp av intervjuer i semistrukturerad form. Analysen visade att kvinnorna hade en medvetenhet om återhämtningens betydelse. Att kunna göra egna val och prioritera var viktigt för återhämtningen och gav dem en känsla av meningsfullhet och att de hade kontroll. Det som främst konkurrerade om utrymmet för återhämtning var arbetet och familjelivet, även om det sistnämnda också gav återhämtning. Det som upplevdes som återhämtande varierade och kunde vara allt från att vila till fysisk aktivitet.</p> / <p>To have a possibility to recover is important for a person's health. Here the focus is on the recovery from work after the working hours, in effect the one that generally happens at our time of leisure. With leisure I anticipate in this context the time that we don't spend working within payed labour. Leisure interests, association commitments, engagements and so forth are activities that compete for our time. It can sometimes be pure recovery but sometimes commitments that increase stress. If room for regeneration is poor or nonexistent there is an increased risk for among other things, stress related troubles. Factors that are decisive for how our recovery and our time of leisure will look, exists on an individual level, in our psychosocial and on a communal level. Today's public health politics focus on decision factors which are "factors in the organization of society and humans living concurrences and living habits that has an impact on good health or poor health". We have different frames to operate in, different resources and we meet and react differently to all kinds of stress factors. According to Aaron Antonovskys, individuals have different levels of resistance. Some remain healthy and manage themselves well, in spite of great demands which have to do with how we handle our obstacles and our ability to give our way of life continuity (SOC, sense of coherence).</p><p> </p><p>The focus on this work is on the recovery and leisure of women, i.e the experience and management of the individual recovery abilities during the leisure time. The purpose with the assignment has been to clarify how (dual) working women experience and manage their recovery opportunities. This to illuminate and create reflection about life situations that maybe to large degree concealed can produce unhealthy outcomes.</p>

<p>A study has been made in CMOS RF-switches that can be used in the front-end of a multi-band radio targeting the 802.11a,b,g and W-CDMA standards and working in the frequency range 2.4-5.5GHz. Especially, one single-transistor switch and two types of transmission gates have been analyzed, simulated and compared with respect to loss, linearity, compression point and noise. From this, five different single-transistor switches have been designed for on-chip probing measurements. Special consideration has been taken to accommodate on-chip testing, thus additional structures have been designed. The simulations and design has been performed with Chartered 0.18um RF-CMOS process. </p><p>The results from the simulations show that the single-transistor switch has better performance in loss, linearity, compression point and noise compared to the transmission gates. However, for the transmission gates the linearity can be increased beyond the linearity of the single-transistor switch if the widths of the transistors are made sufficiently large. </p><p>For the single-transistor switch, simulation results show that the transistor length shall be kept to its minimum for best performance and that the number of fingers does not influence significantly. Also, there are optimum values for the loss in on-mode, the noise and the linearity and worst-case values for the loss in off-mode when the transistor width is varied. Consequently, the single- transistor switch can be tuned by its transistor width to accommodate desired performances.</p>

<p>Sammanfattning:</p><p>De ökande testdatavolymerna som krävs för att testa moderna System-On-Chip (SOC) bidrar i hög grad till den ökande produktionskostnaden. De stora testdatavolymerna kräver stora och dyra Automatic Test Equipment-minnen (ATE-minnen). För att minska behovet av dessa minnen så har olika komprimeringsmetoder utvecklats.</p><p>Denna rapport beskriver arbetet med att implementera en given komprimeringsmetod för testdata till SOC. Den metod som används heter vector repeat och den implementeras genom skapandet av ett för ändamålet avsett dataprogrogram. För att vector repeat ska fungera effektivt så förutsätts det att in- och utgångarna på den ATE som används kan delas in i olika portar. Portarna används för att korta ner testdatats vektorer, vilket möjliggör en bättre komprimering. Resultaten av implementationen har verifierats med hjälp av experiment där testdata från en benchmark SOC använts och jämförts med okomprimerat testdata samt ytterliggare en komprimeringsmetod som heter 9C. Resultaten visar att vector repeat är en effektiv komprimeringsmetod om antalet portar är tillräckligt stort. Experiment har även genomförts som visar hur mycket komprimeringen förbättras då antalet portar som används ökas.</p><p>Dessa resultat kan användas i framtida arbeten, varav ett exempel är, där kostnaden för ökat antal portar tas i beaktande.</p> / <p>Abstract:</p><p>The increased volume of test data which is required in testing of modern System-On-Chip (SOC) are a high contributor to the increased production costs. The large volumes of test data requires large and expensive Automatic Test Equipment memories. (ATE memories). To decrease the need of these memories, different compression methods have been developed.</p><p>This report describes the work with implementing a given compression method for test data to SOC. The method which is used is called vector repeat and it is implemented through the creation of a, for the task designated, computer program.</p><p>If vector repeat should work efficiently it is assumed that the entrances and the exits on the ATE can be divided into different ports. The ports are being used to shorten the vectors of the test data, which enables a better compression. The result of the implementation has been verified through experiments where the test data from a benchmark SOC is used and compared with uncompressed data and another compression method which is called 9C. The result shows that vector repeat is an effective compression method if the number of ports is large enough. Experiments has also been done which show how much the compression is improved when the number of ports in use are increasing.</p><p>These results can be used in future works, where one example is, where the cost of the increasing number of ports is considered.</p>