Tunnelbanan är ett mycket viktigt transportmedel i Stockholm som är igång större delen av dygnet. Tunnelbanans Röda och Blå linjer använder sig av ett äldre signalsystem från 60-talet. Det system som används för signaleringen av de två linjerna är av typen växelströmspårledning med kodning och använder reläställverk. Spårledningarna som detekterar positionen av olika tåg på spåret använder frekvensen 75 Hz. Vid konverteringen av frekvensen 50 Hz till 75 Hz, uppstår koldamm och värmeförluster till utrymmet från frekvensomformaren. Koldammet som avges i luften riskerar att påverka reläfunktionaliteten när det tränger in i relähöljet och sätter sig på ytan för reläkontakterna i utrymmet bredvid frekvensomformare. Trafikförvaltningen har planer på att upprusta Röda linjens signalsystem för att kunna använda dess signalsystem i ytterligare 25 år. Spårledningssystemet positionerar och ger hastighetsbesked till tågen. En litteraturstudie har genomförts kring uppbyggnad av spårledningssystemet och tidigare forskning har utförts kring frekvensomformare för att hitta en ny frekvensomformare som inte riskerar reläfunktionaliteten. Genom faktainsamling från Trafikförvaltningen har nya lämpliga frekvensomformare som kunde ersättas mot de befintliga undersökts. Statiska frekvensomformare har analyserats. Enligt kraven från Trafikförvaltningen identifierades fyra produkter från olika leverantörer. Ingen av de statiska frekvensomformare var direkt kompatibel med befintligt system med anledningen av att systemet är byggd för ett roterande frekvensomformare. ”HZ-50-1105” från GoHz denna modell finns i 1-fas in- respektive 1-fas utmatning. ”FR-D 700” från Mitsubishi och ”Micromaster 440” från Siemens som hade lika användnings funktion det gjorde att de var lik varandra. ”ACS-150” från ABB denna modell hade som max märkeffekt upp till 4 kVA, vilket passar bara för frekvensomformare med märkeffekt 2.5 kVA. De olika typerna av statiska frekvensomformare belastade nätet på ett asymmetriskt sätt. Därför var det viktigt att kunna fördela lasten så jämnt som möjligt på varje fas. Det var svårt att kunna rangordna de valda produkterna utan det bara visades vilka valmöjligheter som fanns vid utbytet av roterande frekvensomformare. Användningen av statiska frekvensomformare eliminera de risker som en roterande frekvensomformare orsakar. Statiska frekvensomvandlare generera olika frekvenser med större noggrannhet samt de har en kortare driftsättnings tid men belastar de nätet asymmetriskt jämfört med roterande frekvensomformare. / The subway is a very important means of transport in Stockholm and is in operation most of the day. The Red and Blue lines of the metro use an older signal system from the 60s. The system used for the signaling of the two lines is of the type AC power line with coding and uses relay switches. The track circuit that detects the position of different trains on the track use the frequency 75 Hz. When converting the frequency 50 Hz to 75 Hz, carbon dust and heat losses is released to the space from the frequency converter. The carbon dust emitted into the air risks affecting relay functionality as it enters the relay housing and settles on the surface of the relay contacts in the space next to the frequency converter. The Traffic Administration have plans to upgrade the Red Line's signaling system in order to use the existing signaling system for another 25 years. The track circuit system positions and gives speed messages to the trains. A literature study has been conducted on the construction of the track circuit system and previous research has been conducted on frequency inverters to safely find a new frequency inverter that does not risk relay functionality. Through fact-finding from the Traffic Administration, new suitable frequency converters that could be replaced with the existing ones were investigated in this research. Static frequency converters were chosen to be investigated. According to the requirements of the Traffic Administration, four products were identified from different suppliers. None of the static frequency converters was directly compatible with existing systems because the system was built for a rotary frequency converter. "HZ- 50-1105" from GoHz this model is available in 1-phase input and 1-phase output respectively. "FR-D 700" from Mitsubishi and "Micromaster 440" from Siemens which were equal in and out connection. "ACS-150" from ABB this model had a maximum rated power up to 4 kVA, which is only suitable for frequency inverters with a rated power of 2.5 kVA. The various types of static frequency inverters loaded the network in an asymmetrical way. Therefore, it was important to be able to distribute the load as evenly as possible on each phase. It was difficult to be able to rank the selected products without just showing the choices that existed when replacing rotary frequency converters. However, the use of static frequency inverters eliminates the risks of a rotating frequency converter. Static frequency converters can more accurately generate different frequencies and they have a shorter commissioning time; however, they load the network asymmetrically compared to rotating frequency converters.

This study separately investigates how temperature as well as two real load-situations affects the modal damping ratio and natural frequencies of a 64.9m span steel arch footbridge. Measurements of acceleration have been completed which covers a temperature span of  to . The natural frequencies of the five investigated modes were observed to decrease 2-6% as the temperature increased. This effect was with the help of beam-theory and finite element modelling deduced to originate mostly from changes in Young’s modulus of the materials, but also geometrical changes in steel because of thermal expansion. Further investigation included a static mass in the form of packed snow that was estimated to weigh 14 tons. The natural frequencies were observed to remain unchanged while the modal damping ratios decreased. The second load-case was an uncontrolled mass-event where a large group of pedestrians travelled over the bridge as two cars stood stationary at the quarter-point of the span. A large increase (146%) of the damping ratio was observed while the natural frequency of the first mode decreased 4%. This change was suggested come from the human structure interaction (HSI) partially because the natural frequency of the human body is close to the first vertical frequency of the bridge thus making humans act like dampers on the bridge when close to resonance, and that the number of pedestrians contribute to the modal mass of the system, thus decreasing the natural frequency. / Denna studie undersöker separat hur temperaturen såväl som två verkliga belastningssituationer påverkar de modala dämpnings kvoterna och egenfrekvenserna hos en 64,9 meter lång stål-bågs gångbro. Mätningar av accelerationen i bron har genomförts som täcker en temperatur på -10°C till 10°C. De naturliga frekvenserna hos de fem undersökta moderna observerades minska 2–6% när temperaturen ökade. Denna minskning var med hjälp av balk-teori och finita element-modellering härled att troligen komma från förändringar i Youngs modul av materialen, men även geometriska förändringar i stålet på grund av termisk expansion. Vidare undersökning innefattade en statisk massa i form av packad snö som uppskattades att väga 14 ton. Egenfrekvenserna observerades förbli oförändrade medan de modala dämpnings kvoterna minskade. Det andra lastfallet var ett okontrollerat massevenemang där en stor grupp fotgängare gick över bron medan två bilar var stationära en fjärdedel in på brons längd. En stor ökning (146%) av dämpnings kvoten för den första vertikala moden observerades medan egenfrekvensen minskade 4%. Denna förändring föreslogs komma från interaktionen mellan människan och bron, delvis för att människokroppens egenfrekvens ligger nära brons första vertikala frekvens vilket gör att människan agerar som en dämpare när de är nära resonans med bron, och att antalet fotgängare bidrar till den modala massan av systemet vilket sänker frekvensen.

As designers began to pack multi-million transistors onto a single chip, their reliance on a global clocking signal to orchestrate the operations of the chip has started to face almost insurmountable difficulties. As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. A middle-of-the-road alternative, which can provide a good performance and avoid the limitations seen in dynamic self-resetting circuits, would be to implement self-resetting behavior in static circuits. This alternative has been introduced recently as Self-Resetting Stage Logic and used to propose three types of clockless pipelines. Experimental studies show that these pipelines have the potential to produce high throughputs with a minimum area overhead if a suitable synthesis methodology is available. This thesis proposes a novel synthesis methodology to design and verify clockless pipelines implemented in SRSL by taking advantage of the maturity of current CAD tools. This methodology formulates the synthesis problem as a combinatorial analytical problem for which a run-time efficient exact solution is difficult to derive. Consequently, a two-phase algorithm is proposed to synthesize these pipelines from gate netlists subject to user-specified constraints. The first phase is a heuristic based on the as-soon-as-possible scheduling strategy in which each gate of the netlist is assigned to a single pipeline stage without violating the period constraint of each pipeline stage. On the other hand, the second phase consists of a heuristic, based on the Kernighan-Lin partitioning strategy, to minimize the number of nets crossing each pair of adjacent pipeline stages. The objective of this optimization is to reduce the number of latches separating pipeline stages since these latches tend to occupy large areas. Experiments conducted on a prototype of the synthesis algorithm reveal that these self-resetting stage logic pipelines can easily reach throughputs higher than 1 GHz. Furthermore, these experiments reveal that the area overhead needed to implement the self-resetting circuitry of these pipelines can be easily amortized over the area of the logic embedded in the pipeline stages. In the overall, the synthesis methods developed for SRSL produce low area overhead pipelines for wide and deep gate netlists while it tends to produce high throughput pipelines for wide and shallow gate netlists. This shows that these pipelines are mostly suitable for coarse-grain datapaths.

To reason about a program means to state or conclude, by logical means, some properties the program exhibits; like its correctness according to certain expected behavior. The continuous need for more ambitious, more complex, and more dependable software systems demands for better mechanisms to modularize them and reason about their correctness. The reasoning process is affected by the design decisions made by the developer of the program and by the features supported by the programming language used. Beyond Object Orientation, Implicit Invocation and Aspect Oriented languages pose very hard reasoning challenges. Important tradeoffs must be considered while reasoning about a program: modular vs. non-modular reasoning, case-by-case analysis vs. abstraction, explicitness vs. implicitness; are some of them. By deciding a series of tradeoffs one can configure a reasoning scenario. For example if one decides for modular reasoning and explicit invocation a well-known object oriented reasoning scenario can be used. This dissertation identifies various important tradeoffs faced when reasoning about implicit invocation and aspect oriented programs, characterize scenarios derived from making choices regarding these tradeoffs, and provides sound proof rules for verification of programs covered by all these scenarios. Guidance for program developers and language designers is also given, so that reasoning about these types of programs becomes more tractable.

The design of high-performance computing architectures requires performance analysis of largescale parallel applications to derive various parameters concerning hardware design and software development. The process of performance analysis and benchmarking an application can be done in several ways with varying degrees of fidelity. One of the most cost-effective ways is to do a coarse-grained study of large-scale parallel applications through the use of program skeletons. The concept of a “program skeleton” that we discuss in this paper is an abstracted program that is derived from a larger program where source code that is determined to be irrelevant is removed for the purposes of the skeleton. In this work, we develop a semi-automatic approach for extracting program skeletons based on compiler program analysis. We demonstrate correctness of our skeleton extraction process by comparing details from communication traces, as well as show the performance speedup of using skeletons by running simulations in the SST/macro simulator. Extracting such a program skeleton from a large-scale parallel program requires a substantial amount of manual effort and often introduces human errors. We outline a semi-automatic approach for extracting program skeletons from large-scale parallel applications that reduces cost and eliminates errors inherent in manual approaches. Our skeleton generation approach is based on the use of the extensible and open-source ROSE compiler infrastructure that allows us to perform flow and dependency analysis on larger programs in order to determine what code can be removed from the program to generate a skeleton.

The field of microfluidics has recently been gathering a lot of attention due to the enormous demand for devices that work in the micro scale. The problem facing many researchers and designers is the uncertainty in using macro scaled theory, as it seems in some situations they are incorrect. The general idea of this work was to decide whether or not the flow through micro diffusers and nozzles follow the same trends seen in macro scale theory. Four testing wafers were fabricated using PDMS soft lithography including 38 diffuser/nozzle channels a piece. Each nozzle and diffuser consisted of a throat dimension of 100µm x 50µm, leg lengths of 142µm, and half angles varying from 0o - 90o in increments of 5o. The flow speeds tested included throat Reynolds numbers of 8.9 -" 89 in increments of 8.9 using distilled water as the fluid. The static pressure difference was measured from the entrance to the exit of both the diffusers and the nozzles and the collected data was plotted against a fully attached macro theory as well as Idelchik's approximations. Data for diffusers and nozzles up to HA = 50o hints at the idea that the flow is neither separating nor creating a vena contracta. In this region, static pressure recovery within diffuser flow is observed as less than macro theory would predict and the losses that occur within a nozzle are also less than macro theory would predict. Approaching a 50o HA and beyond shows evidence of unstable separation and vena contracta formation. In general, it appears that there is a micro scaled phenomenon happening in which flow gains available energy when the flow area is increased and looses available energy when the flow area decreases. These new micro scaled phenomenon observations seem to lead to a larger and smaller magnitude of pressure loss respectively.

Motivated by our frustration with the lack of quantum chemistry methods for strongly-correlated open-shell systems, we develop quantitative methods for computing the electronic structure of such systems and qualitative tools for analyzing their chemical properties and reactivity. Specifically, we present a modern framework for performing sparse configuration interaction (CI) computations with arbitrary (Slater determinant) N-electron basis sets, using restricted or generalized spin-orbitals, and including computation of spin-polarized 1- and 2- electron reduced density matrices (RDMs). This framework is then used to implement the flexible ansätze for N-electron CI (FanCI) method more efficiently, via increased vectorization in the FanCI equations and use of sparse CI algorithms. We also extended the FanCI approach, including least-squares and stochastic optimization techniques, the computation of spin-polarized 1- and 2- electron RDMs, and transition energies (ionization potentials, electron affinities, and excitation energies). We use these tools to compare various open-shell CI methods and FanCI methods based on various antisymmetrized product of nonorthogonal geminals ansätze. To translate the vast amount of quantitative data present in the energies and (spin-polarized) density matrices of multiple open-shell states, we present a new, internally consistent and unambiguous framework for spin-polarized conceptual density-functional theory (SP-DFT) that reduces to a sensible formulation of spin-free CDFT in an appropriate limit. Using this framework, we were able to generalize the (non-spin-polarized) Parr function. We can also, using this framework, construct promolecules with proatoms having non-integer charges and multiplicities. Finally, we describe an equations-of-motion-based method for computing spin-polarized reactivity descriptors of a chemical system from only the ground state energy and the 1- and 2- electron RDMs from a single-point electronic structure computation, and show some benchmark computations for this method based on various CI and FanCI electronic structure methods. / Thesis / Doctor of Philosophy (PhD)

Vale is a multi-purpose programming language that focuses on guaranteeing memory safety with minimal effect on performance. To accomplish this, Vale utilizes a memory management system called Hybrid Generational Memory (HGM). HGM uses generational references to track the state of objects in memory, and static analysis to reduce memory management overhead at runtime. This thesis describes the program that performs static analysis on Vale source code during compilation, and analyzes its effect on the performance of Vale programs.

This thesis describes the design and evaluation of two devices to be included in the next generation of the family of devices called the Boundary Layer Data System (BLDS). The first device, called the Quasi-Static Strain Data Acquisition System, is a continuation of the BLDS-M series of devices to be known as the Flight Test Data System (FTDS) that uses a modular approach to acquire non-flow, quasi-static mechanical strain measurements. Various breakout boards and development boards were used to synthesize the device, which were housed by a custom PCB board. The system is controlled by the SimbleeTM System on a Chip (SOC), and strain measurements are acquired using the HX711 analog-to-digital converter (ADC), and acceleration measurements are acquired with the ADXL345 accelerometer. The Arduino IDE was used to program and troubleshoot the device. The second device, called the Dynamic Strain Data Acquisition System, is a laboratory proof-of-concept device that evaluates various methods of acquiring dynamic strain measurements that may be used in future FTDS designs. A custom PCB board was designed that houses the microcontroller and the various passive components and ICs used to acquire and store strain measurements. The system is controlled by the Atxmega128A4U microcontroller, and measurements are acquired using the AD7708 external ADC and the on-board ADC of the microcontroller. Atmel StudioTM was used to program the microcontroller in C/C++ and to troubleshoot the device. Both devices were tested extensively under room temperature and low temperature conditions to prove the reliability and survivability of each device. The quasi-static data acquisition system was validated to acquire and store measurements to a microSD card at 10 Hz, with a peak operating current under 60 mA. The dynamic data acquisition system was proven to acquire a thousand measurements at 1 kHz and store the data to a microSD card, with a peak operating current under 60 mA.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM