Les technologies SOI partiellement désertées (PD-SOI), permettent de gagner en performances ou en consommation dynamique, par rapport à leur équivalent sur substrat massif (BULK). Leur inconvénient principal est la consommation statique qui est bien supérieure, en raison principalement de l'effet de body flottant de ses transistors. Ce travail propose une technique de réduction de la consommation statique, pour la technologie PD-SOI, basée sur le principe des interrupteurs de puissance. Un nouveau facteur de mérite recherchant le meilleur compromis entre vitesse, courant de fuite et surface est introduit pour la sélection du meilleur interrupteur de puissance. L'interrupteur de puissance proposé apporte par rapport à une solution de référence, et pour le même courant de fuite en mode éteint, une réduction de la résistance équivalente en mode passant de 20%. Les tests comparatifs sur Silicium de blocs LDPC incluant ces montages montrent, entre PD-SOI et BULK, un gain de 20% en vitesse pour la même tension d'alimentation, une réduction de 30% de la consommation dynamique pour la même vitesse et une division par 2 de la consommation statique. Enfin, une bascule de rétention, élément à associer aux interrupteurs de puissance, optimisée pour le PD-SOI, est proposée. Cette bascule est conçue de manière robuste et peu fuyante. / Partially depleted SOI technologies (PD-SOI), offer advantages in terms of speed and dynamic power consumption compared to bulk technologies. The main drawback of the PD-SOI technology is its static power consumption, which is higher than bulk one. It is due to the floating body of its transistors. This work presents a new static power consumption design technique based on power switches. A new factor of merit is introduced selecting the power switch with the best trade-off in terms of leakage current, speed and area. A new power switch brings, in comparison to a reference solution, a reduction of 20% of the ON mode equivalent resistance for the same OFF mode leakage current PD-SOI Silicon validation test chips include LDPC bloc supplied by the proposed solution. Comparing to the bulk technology, a speed gain of 20% is measured for the same voltage supply and a dynamic power consumption reduction of 30% at same speed is achieved. This solution allows reducing by 2 the static power consumption. Finally, a retention flip-flop associated to the implementation of power switches and optimized in PD-SOI is proposed. This flip-flop is designed to be robust with a low leakage current.

Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

A melhora da confiabilidade em redes de distribuição de energia elétrica é um tema importante para as indústrias de fornecimento de eletricidade, devido aos regulamentos estritos em muitos países. Depois de uma falha na rede, algumas chaves são usadas para isolar a falha, enquanto outras restauram a energia a alguns consumidores. A ótima seleção das chaves que serão abertas ou fechadas para restaurar a energia é conhecido como o problema de restauração de serviço. A instalação de chaves em posições estratégicas pode reduzir o tempo de parada, e assim melhorar a confiabilidade da rede. A seleção ótima de posições para instalar chaves é conhecido como o problema de alocação de chaves. Estes dois problemas estão relacionados estreitamente. Esta dissertação estuda o problema de alocação de chaves, considerando o problema de restauração de serviço como um subproblema. Dois métodos são propostos para estimar a confiabilidade de uma rede de distribuição com um conjunto dado de chaves instaladas. O foco principal está nas heurísticas para resolver o problema composto. Propõe-se aqui métodos como busca tabu, procedimento de busca gulosa adaptativa aleatória (sigla em inglês: GRASP), e procedimento iterativo de construção por amostras com reconexão de caminhos. Também estuda-se o benefício dos métodos de construção gulosa, semigulosa, aleatória e por amostras, e estuda-se o desempenho das estratégias de busca local por amostras, primeira melhoria e melhor melhoria. Os diferentes métodos são comparados e analisados. Os resultados mostram que os métodos por amostras são baratos e levam a soluções de boa qualidade. O procedimento iterativo de construção por amostras com reconexão de caminhos é o melhor método proposto para resolver o problema composto que é proposto nesta dissertação. / The improvement of reliability in electrical power distribution networks is an important issue for electricity supply industries, due to strict regulations in many countries. After a failure in the network, some switches are used to isolate the failure, while others restore the energy to some consumers. The optimal selection of the switches to open or close to restore energy is called the service restoration problem. The installation of switches in strategic places may reduce the outage time in case of blackouts, and thus improve the reliability of the network. The optimal selection of places to install switches is called the switch allocation problem. These two problems are closely related. This dissertation studies the switch allocation problem, considering the service restoration problem as a sub-problem. Two methods are proposed to estimate the reliability of a distribution network with a given set of installed switches. The main focus is in heuristics to solve the joint problem. It proposes methods like tabu search, greedy randomized adaptive search procedure, and iterated sample construction with path relinking. It also studies the benefit of greedy, semigreedy, random, and sample construction methods, and studies the performance of sample, first improvement and best improvement local search strategies. The different methods are compared and analyzed. The results show that sample approaches are inexpensive and lead to solutions of good quality. Iterated sample construction with path relinking is the best method to solve the joint problem that is proposed in this dissertation.

Made available in DSpace on 2018-08-02T00:01:06Z (GMT). No. of bitstreams: 1 tese_6875_Dissertação_Rafael_Campanharo_Favoreto_Versão_Final.pdf: 6258201 bytes, checksum: bed370fa569f7f0c60e71f03e2c28a5e (MD5) Previous issue date: 2014-08-22 / As demandas por serviços de telecomunicações multimídia, garantia de QoS (Quality of Service) e mecanismos de gerenciamento e controle direcionam a evolução da rede de núcleo para adoção da tecnologia OTN (Optical Transport Network) como solução de rede de transporte. Para conduzir a evolução da tecnologia OTN a ITU-T (International Telecommunication Union Telecommunications Standardization Sector) estabelece uma série de recomendações, dentre elas, as específicas para o plano de gerenciamento de redes. Essas, por sua vez, apresentam deficiências no que se referem ao levantamento do inventário dos objetos gerenciados definidos pelas normas da ITU-T. A ITU-T define a representação dos elementos de rede em caráter funcional, mais especificamente como módulos de Funções Atômicas. Contudo, a falta de clareza na implementação das Funções Atômicas e a carência de integração com as representações físicas dos elementos de rede implica na omissão, por parte dos diversos fabricantes, da implementação dos mecanismos recomendados em norma. Esta dissertação tem como objetivo geral apresentar uma proposta de solução para o levantamento do inventário dos elementos de rede em redes OTN abrangendo de forma integrada as representações funcional e física do elemento de rede, além de possibilitar aos diversos fabricantes a aderência às normas da ITU-T bem como oferecer ao operador de rede a configuração dos componentes de uma forma mais intuitiva.

Orientador: Shusaburo Motoyama / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-06T21:11:41Z (GMT). No. of bitstreams: 1 Santos_CarlosRobertodos_D.pdf: 1522457 bytes, checksum: 0ab724ca4cf14d30cac5a6eadc2e5fb7 (MD5) Previous issue date: 2006 / Resumo: Neste trabalho é proposto um comutador de pacotes baseado em uma estrutura crossbar com m enlaces paralelos internos, denominado comutador CEP (Comutador Crossbar de Enlaces Paralelos), e com facilidade para prover qualidade de serviço (QoS ¿ Quality of Service). O comutador proposto utiliza uma combinação de filas na entrada e na saída. Os pacotes são transferidos dos buffers de entrada para os buffers de saída através de mxN linhas internas. Como as linhas internas e externas operam com a mesma velocidade, não há necessidade de aumentar a velocidade do clock interno, fazendo com que a estrutura proposta seja apropriada para comutadores de alta velocidade. O desempenho do comutador CEP é analisado admitindo pacotes de tamanho fixo (célula ATM) e pacotes de tamanho variável. O tempo médio de atraso dos pacotes e o tamanho médio das filas de entrada e de saída são avaliados por simulação e/ou por modelos analíticos, utilizando teoria de filas / Abstract: A QoS (Quality of Service) provisioned CIOQ (Combined Input Output Queuing) switch using crossbar structure with m parallel lines per output port is proposed in this work. The packets at input buffers are transferred to the output buffers by means of mxN internal lines. Since all internal lines have the same speed as external links, no internal clock speedup is required so that the proposed structure is suited for high-speed switches. Switch models for analysis are proposed for both fixed and variable packet lengths and their performances, in terms of average packet waiting time and average queue size for both input and output buffers, are evaluated by simulation and/or analytically by means of queuing theory. The proposed switch also presents a feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of service / Doutorado / Telecomunicações e Telemática / Doutor em Engenharia Elétrica

Reconfigurable antennas are attractive for many military and commercial applications where it is required to have a single antenna that can be dynamically reconfigured to transmit or receive on multiple frequency bands and patterns. RF-MEMS is a promising technology that has the potential to revolutionize RF and microwave system implementation for next generation telecommunication applications. Despite the efforts of top industrial and academic labs, commercialization of RFMEMS switches has lagged expectations. These problems are connected with switch design (high actuation voltage, low restoring force, low power handling), packaging (contamination layers) and actuation control (high impact force, wear, fatique). This Thesis focuses on the design and control of a novel ohmic RF-MEMS switch specified for reconfigurable antennas applications. This new switch design focuses on the failure mechanisms restriction, the simplicity in fabrication, the power handling and consumption, as well as controllability. Finally, significant attention has been paid in the switch’s electromagnetic characteristics. Efficient switch control implies increased reliability. Towards this target three novel control modes are presented. 1) Optimization of a tailored pulse under Taguchi’s statistical method, which produces promising results but is also sensitive to fabrication tolerances. 2) Quantification of resistive damping control mode, which produces better results only during the pull-down phase of the switch while it is possible to be implemented successfully in very stiff devices. 3) The “Hybrid” control mode, which includes both aforementioned techniques, offering outstanding switching control, as well as immunity to fabrication tolerances, allowing an ensemble of switches rendering an antenna reconfigurable, to be used. Another issue that has been addressed throughout this work is the design and optimization of a reconfigurable, in pattern and frequency, three element Yagi-Uda antenna. The optimization of the antenna’s dimensions has been accomplished through the implementation of a novel technique based on Taguchi’s method, capable of systematically searching wider areas, named as “Grid-Taguchi” method.

A partially parallel reconfigurable channel switch is constructed for use in DFBR. Its permutation can be changed while running without any interruption in the streams of data. Three approaches are tried: one based on asorting network, one based on memories and multiplexers and one based on a Clos network. Variants with the pattern stored in memories and in shift registers are tried. They are implemented in automatically generated Verilog and synthesized for an FPGA. Their cost in terms of area use, memory use and maximum clock frequency is compared and the results show that the Clos based approach is superior in all aspects and that pattern data should not be saved in shift registers. The work is open source and available for download at https://github.com/channelswitch/channelswitch. / En delvis parallel och delvis seriell kanalswitch för användning inom DFBR skapas. Dess permutation kan ändras medan den kör utan avbrott i dataströmmen. Tre alternativ undersöks: ett baserat ett sorteringsnätverk, ett baserat på minnen och multiplexrar och ett som baseras på Clos-nätverk. Versioner med mönsterdata sparad i skiftregister och i minnen prövas. De implementeras i automatiskt genererad Verilog och synthesiseras för en FPGA. Deras kostnad i areaanvändning, minnesanvändning och maximal klockfrekvens jämförs. Resultaten visar i princip att Clos-nätverken är bäst i alla avseenden och att mönsterdata ska sparas i RAM-minnen och inte i skiftregister. Arbetet är open source och kan laddas ner från https://github.com/channelswitch/channelswitch.

The evolving technology has over the past decade contributed to a bandwidth explosion on the Internet. This makes it interesting to look at the development of the workhorses of the Internet, the core routers. The main objective of this project is to develop a 16 port gigabit core router architecture using intellectual property (IP) blocks and a SoCBUS on-chip interconnection network. The router architecture will be evaluated by making simulations using the SoCBUS simulation environment. Some changes will be made to the current simulator to make the simulations of the core router more realistic. By studying the SoCBUS network load the bottlenecks of the architecture can be found. Changes to the router design and SoCBUS architecture will be made in order to boost the performance of the router. The router developed in this project can under normal traffic conditions handle a throughput of 16x10Gbit/s without dropping packets. This core router is good enough to compete with the top of the line single-chip core routers on the market today. The advantage of this architecture compared to others is that it is very flexible when it comes too adding new functionality. The general on-chip network also reduces the design time of this system.

A piezoelectric energy harvesting (PEH) system can harvest electrical energy from ambient vibration energy. In a PEH system, the interface rectifier circuit is critical because it converts AC from the output of piezoelectric harvester to DC that can power the load. Hence, improving the efficiency of the interface circuit can directly increase the efficiency of the entire PEH system; consequently, more power can be harvested. Commonly used interface circuits in PEH systems, such as full-bridge and voltage- doubler rectifiers,lead to relatively simple circuit implementations but they show serious limitations in energy-harvesting efficiency. Several innovative solutions have been reported to improve the efficiency of the interface rectifiers, such as ‘switch-only’ and ‘bias-flip’ techniques [7]. Such solutions utilize additional switches or switched inductors to speed up and even quickly reverse (flip) the voltage on the rectifier input to the desired voltage-level and condition for energy transfer, ultimately improving the overall efficiency of the energy harvesting. However, such techniques rely on accurate timing and synchronization of the pulsed switches every time the current produced by the piezoelectric harvester changes polarity. This thesis studies and investigates the impact of the non-ideal switching effects on the energy efficiency of the switch-only and bias-flip interface rectifiers in a PEH system, by theoretical derivation and experimental simulation.

Many genes demonstrate highly dynamic pulsatile expression, with characteristic bursts of activity. Dynamic expression of the human prolactin (hPrl) gene in pituitary cells has previously been investigated identifying key temporal characteristics, influenced by the process of chromatin remodelling. Earlier work on the related pituitary human growth hormone (hGH) proximal promoter (-496/+1bp) indicated that it displayed similar dynamic behaviour. The human GH gene contains an extensive long-distance regulatory sequence, including a locus control region (-14/-32kbp) that has been shown to regulate chromatin remodelling and confer tissue-specificity of hGH expression. In this work I aimed to study dynamic regulation of the hGH gene promoter in detail. Initially I investigated the efficiency of several methods to express the luciferase gene in a 180kb hGH genomic fragment using bacterial artificial chromosome recombineering, to allow the investigation of single cell transcription dynamics. Although a functional recombinant BAC was not finalised during the course of the work, I carried out detailed time course studies using shorter hGH-reporter constructs. Using quantitative microscopy to study live single cells, I compared the dynamic characteristics of a 5kb hPrl promoter fragment with those of -840/+1bp and -3348/+1bp hGH-luciferase promoter-reporter constructs. Whilst previous hPrl analysis utilised a binary mathematical model assuming a simplified two-state (ON/OFF) process of gene transcription, I validated and applied a novel stochastic switch model (SSM), assuming instead that transcription rate can switch between any variable states at any time. Through doing so I observed an asymmetry in transcription rate switching, suggesting an all-or-nothing activation of a single UP-switch, with a greater number of rate decreasing DOWN-switches. The -3348/+1bp construct produced double the number of DOWN-switches, whilst the -840/+1bp construct produced 1.5 DOWN-switches in a 48h period. The cycling of transcriptional activity seen by the shorter construct was modified through the addition of forskolin, activating cAMP signalling. However, significant modification of the transcriptionally inactive refractory period seen with the -3348/+1bp construct (reduced from 3h to 1.9h) required histone modification through application of trichostatin A, a HDAC inhibitor. In conclusion, different promoter elements confer different transcriptional timing and dynamics. A subtler transcriptional modelling, such as used here in the SSM, reveals new insights into the phenomena of transcriptional switching, but the mechanisms involved remain to be determined.