Architectures reconfigurables dynamiquement offrent théoriquement excellent compromis entre performance et flexibilité. Pratiquement, ces architectures sont basées sur un ou plusieurs processeurs et plusieurs cellules reconfigurables. Une cellule reconfigurable peut charger, exécuter et décharger des accélérateurs matériels. Cette propriété permet la virtualisation des tâches matérielles. Dans ce contexte, une application peut prendre avantage de la flexibilité du logiciel et la performance du matériel. Dans les architectures reconfigurables actuels, les tâches matérielles sont limitées à une coopérative multi-tâches , depuis le temps de reconfiguration et l'heure de contexte stockage sont coûteux . Bien que le temps de reconfiguration est dépendante de l’architecture, le temps requis pour stocker ou restaurer le contexte dépend fortement des applications s'exécutant sur des tâches matériels. La réduction de ce temps des changements de contexte est obligatoire d'offrir à la tâche matérielle d'un multi- tâches préemptif, tout comme les tâches de logiciels. Plusieurs méthodes existent pour effectuer les opérations contexte commutateur matériel dans un contexte cellulaire homogène : chaîne de relecture dédiée sur tissus reconfigurables, des points de contrôle, de numérisation de la chaîne sur le contexte réel. Mais, rien n'a été proposé dans un contexte de tissu hétérogène (par exemple une accélération matérielle nuage fournir sur différents types de carte FPGA) .L'objectif de cette thèse est de proposer de nouvelles méthodes et algorithmes pour permettre le matériel des changements de contexte, même entre des cibles matérielles hétérogènes. Au cours de la thèse, l'étudiant devra :- Réaliser une bibliographie sur les méthodes du matériel du groupe de préemption existants dans le contexte cellulaire homogène.- Proposer des algorithmes qui permettent une solution légère et générique changement de contexte pour les tâches matérielles .- Valider ces algorithmes par leur intégration dans un flux de production d' accélérateur matériel . Ainsi, le flux prolongée peut générer, en plus de la tâche matérielle d'une application, le support matériel dédié pour des changements de contexte.- Proposer une stratégie de génération (multi- cible supplémentaire, ...) adapté pour cibles hétérogènes. La stratégie doit préserver les points de synchronisation entre les objectifs- Prototype de preuve de concepts sur la stratégie sur un nuage de FPGA. / Dynamically reconfigurable architectures offer theoretically excellent trade-off between performance and flexibility. Practically, these architectures are based on one or several processors and several reconfigurable cells. A reconfigurable cell can load, execute and unload hardware accelerators. This property enables virtualization of hardware tasks. In this context, an application can take benefit from both software flexibility and hardware performance. In current reconfigurable architectures, hardware tasks are limited to cooperative multi-tasking, since reconfiguration time and context-storing time are expensive. While reconfiguration time is architecture-dependent, the time required to store or restore the context strongly depends on applications running on hardware tasks. Reducing this context-switch time is mandatory to offer to hardware task a preemptive multi-tasking, just like software tasks. Several methods exist to perform the hardware context-switch operations in an homogeneous cell context: dedicated readback chain on reconfigurable fabrics, checkpoints, scan-chain on live context. But, nothing has been proposed in an heterogeneous fabric context (e.g. a cloud providing hardware acceleration on various kind of FPGA board).The goal of this thesis is to propose new methodologies and algorithms to enable hardware context-switch even between heterogeneous hardware targets. During the thesis, the student will have to:- Realize a bibliography on the existing hardware task preemption methods in homogeneous cell context.- Propose algorithms that enable a lightweight and generic context switch solution for hardware tasks.- Validate these algorithms by their integration in a hardware accelerator generation flow. Thus, the extended flow can generate in addition of the hardware task of an application, the dedicated hardware support for context-switch.- Propose an generation strategy (incremental, multi-target,...) suitable for heterogeneous targets. The strategy has to preserve synchronization points between targets- Prototype proof-of-concepts on the strategy on an FPGA cloud.

abstract: Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self-healing capability, which depends on the applied healing voltage and the current limit. However, they fail at lower current densities than metal interconnects due to an ion-drift induced failure mechanism. The results on the PMC based switches demonstrate that a model comprising a Schottky diode in parallel with a variable resistor predicts the behavior of the device. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

Le CEA-Leti propose des transistors bidirectionnels courant-tension sur base de la technologie récente HEMT GaN récemment appliquée à l’interrupteur de puissance. La caractéristique bidirectionnelle 4 segments ouvre de nouvelles perspectives en termes de structures d’électronique de puissance et amène à explorer les topologies qui requièrent ce type d'interrupteurs afin de permettre la conversion AC/DC ou AC/AC mono-étage. Ces structures, qui requièrent alors moins d’interrupteurs, permettent potentiellement de gagner en termes de compacité et de rendement. Les interrupteurs 4 segments CEA Leti ont la particularité d’être mono-grille, ce qui permet le pilotage d’un de ces interrupteurs avec un seul signal de commande. En revanche, cette spécificité amène à laisser de côté des stratégies de commande classique et à explorer de nouveaux modes de contrôle : dans ce cadre, ce travail de thèse s’est intéressé à des stratégies de commutation automatiques appliquées à l’interrupteur bidirectionnel mono-grille. Un « cadre de commutation » spécifique a été définit comme prérequis à la définition de toute topologie implémentant ce type d’interrupteur afin de mettre en œuvre des stratégies d’auto-commutation de type ZCS ou bien ZVS. Sur cette base, deux topologies, l’une ZCS, l’autre ZVS, ont été étudiées dans le cadre d’une conversion AC/DC avec fonction PFC et réversibilité en puissance. La topologie à commutations ZVS a été privilégiée pour une mise en œuvre expérimentale. Dans cette perspective, un circuit de driver capable de générer des auto-commutations ZVS a été conçu. Le fonctionnement du convertisseur en auto-commutations ZVS est validé par des essais sur un prototype en fonctionnement AC/DC. / CEA-Leti offers bidirectional current-voltage transistors based on the HEMT GaN technology recently applied to the power switch design. The 4-segment bidirectional feature opens new perspectives in terms of power electronics structures and leads to explore the topologies that require this type of switches, allowing to design single-stage AC-DC or AC-AC conversion systems. These structures, which then require fewer switches, offer potential benefits in terms of compactness and efficiency. The 4-segment CEA Leti switch has the particularity of being single-gate type, which allows to control one bidirectional switch with just one control signal. On the other hand, this specificity leads to avoid classical control strategies and to explore new modes of control: in this context, this thesis work was interested in automatic switching strategies applied to the single gate bidirectional switch. A specific "switch frame" has been defined as a preliminary condition for the definition of any topology implementing this type of switch in order to implement ZCS or ZVS self-switching strategies. On this basis, two topologies, one ZCS, the other ZVS, were studied in the context of an AC/DC conversion with PFC function and power reversibility. The ZVS switching topology has been selected for experimental implementation. In this perspective, a specific ZVS auto-switching driver circuit has been designed. The converter operation, in ZVS auto-switching, is validated by tests on a prototype in AC/DC conversion mode.

A melhora da confiabilidade em redes de distribuição de energia elétrica é um tema importante para as indústrias de fornecimento de eletricidade, devido aos regulamentos estritos em muitos países. Depois de uma falha na rede, algumas chaves são usadas para isolar a falha, enquanto outras restauram a energia a alguns consumidores. A ótima seleção das chaves que serão abertas ou fechadas para restaurar a energia é conhecido como o problema de restauração de serviço. A instalação de chaves em posições estratégicas pode reduzir o tempo de parada, e assim melhorar a confiabilidade da rede. A seleção ótima de posições para instalar chaves é conhecido como o problema de alocação de chaves. Estes dois problemas estão relacionados estreitamente. Esta dissertação estuda o problema de alocação de chaves, considerando o problema de restauração de serviço como um subproblema. Dois métodos são propostos para estimar a confiabilidade de uma rede de distribuição com um conjunto dado de chaves instaladas. O foco principal está nas heurísticas para resolver o problema composto. Propõe-se aqui métodos como busca tabu, procedimento de busca gulosa adaptativa aleatória (sigla em inglês: GRASP), e procedimento iterativo de construção por amostras com reconexão de caminhos. Também estuda-se o benefício dos métodos de construção gulosa, semigulosa, aleatória e por amostras, e estuda-se o desempenho das estratégias de busca local por amostras, primeira melhoria e melhor melhoria. Os diferentes métodos são comparados e analisados. Os resultados mostram que os métodos por amostras são baratos e levam a soluções de boa qualidade. O procedimento iterativo de construção por amostras com reconexão de caminhos é o melhor método proposto para resolver o problema composto que é proposto nesta dissertação. / The improvement of reliability in electrical power distribution networks is an important issue for electricity supply industries, due to strict regulations in many countries. After a failure in the network, some switches are used to isolate the failure, while others restore the energy to some consumers. The optimal selection of the switches to open or close to restore energy is called the service restoration problem. The installation of switches in strategic places may reduce the outage time in case of blackouts, and thus improve the reliability of the network. The optimal selection of places to install switches is called the switch allocation problem. These two problems are closely related. This dissertation studies the switch allocation problem, considering the service restoration problem as a sub-problem. Two methods are proposed to estimate the reliability of a distribution network with a given set of installed switches. The main focus is in heuristics to solve the joint problem. It proposes methods like tabu search, greedy randomized adaptive search procedure, and iterated sample construction with path relinking. It also studies the benefit of greedy, semigreedy, random, and sample construction methods, and studies the performance of sample, first improvement and best improvement local search strategies. The different methods are compared and analyzed. The results show that sample approaches are inexpensive and lead to solutions of good quality. Iterated sample construction with path relinking is the best method to solve the joint problem that is proposed in this dissertation.

Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

S’inscrivant dans le cadre de la gestion de l’énergie dans l’habitat du programme SESAME du pôle de compétitivité S2E2, l’objectif de cette thèse est d’étudier et de proposer une structure d’interrupteur commandable à l’ouverture et à la fermeture, bidirectionnel en tension et en courant et à faible perte énergétique, destiné à connecter tout type de charges sur le réseau alternatif 230V/50Hz. Il n’existe pas à l’heure actuelle de composants interrupteurs monolithiques de ce type. La première partie du mémoire présente les interrupteurs électroniques existants. La deuxième partie, traite des interrupteurs électroniques à base de transistors MOS et des limites de cette technologie unipolaire en termes de compromis de minimisation de surface de puces et de minimisation de la dissipation de puissance. Nous montrons ensuite que l’on peut repousser ces limites en adoptant des solutions à base de transistors bipolaires de puissances et notamment avec des bases fines autoprotégées (Transistors GAT). Le quatrième chapitre présente les résultats d’une étude des caractéristiques à l’état passant et à l’état bloqué de transistors GAT et valide leur aptitude à fonctionner sur le réseau alternatif. Nous montrons plusieurs voies possibles d’amélioration des caractéristiques de ces transistors avant d’étudier leur comportement dans une fonction interrupteur. Nous terminons ce travail en démontrant l’intérêt de la commande des transistors GAT en mode de conduction inverse, intérêt qui nous conduit ensuite à proposer une structure d’interrupteur totalement novatrice, avec la réduction par deux du nombre de composants et donc une réduction accrue de la puissance dissipée dans l’interrupteur. / As part of the energy management for household appliances of the S2E2 competitive pole SESAME program, the objective of this thesis is to propose a bidirectional switch in current and voltage with full turn-off control and low energy loss, ensuring the control of all loads types connected to the mains. The first part of this thesis presents the advantages and disadvantages of discrete or monolithic switches. In the second part, we were interested in electronic switches composed of MOS transistors. Different associations strategies and controls will be tested to reduce the power dissipation of the switch on the one hand, and facilitate control of the device on the other hand. Then we turned to solutions based on power bipolar transistors. The last one, called GAT distinguished itself by its high current gain and its low voltage drop in the on state. By implementing around the active base heavily doped caissons which create a shielding effect, one can increase the structure performances. After the design of this component in our laboratory, the characteristics of the on state and the off state were improved to validate its functionality in AC mains. The study will then focus on different technologies to confirm its performances. Using low metallization resistance and assembly strategy intelligently defined, it has been demonstrated that the performance of this component can be increased. Finally, we proposed a new switch structure using only two transistors GAT. We show that the interesting GAT reverse mode characteristics permit to deflect the load current flowing in the diodes and delete them. So we reduced the important source of power dissipation in the switch.

The aim of this thesis is to characterize metabolic changes in hemocytes during the immune response in D. melanogaster using in vivo markers as well as by measuring gene expression. The impact of the transcription factor HIF1 on the gene expression of glycolytic enzymes and its impact on the systemic metabolism was evaluated. The importance of HIF1 and LDH in the process of fighting against S. pneumoniae infection was tested as well.

Ett verktyg har utvecklats i programmeringsspråket Python, som analyserar status för uppkopplingar hos Fibre to the X (FTTX)-kunder i Telias nät. Systemet består av en moduluppdelad struktur, där alla analysfunktioner av samhörande typer är uppbyggda i egna moduler. Alla moduler lagras som individuella kodfiler. Systemet är designat för att enkelt kunna vidareutvecklas genom att tillägga fler analysmoduler i framtida projekt. För att utföra en analys på en specifik kund, hämtar systemet tekniska dataparametrar via den switch som kunden sitter uppkopplad mot. Dessa parametrar jämförs därefter med förbestämda värden för att hitta avvikelser. Simple network management protocol (SNMP) och Telnet är de primära protokollen som används för att hämta relevant data. Systemet har enbart Hypertext Transfer Protocol (HTTP) som input och output. Resultatet av en analys, redovisas som Extensible Markup Language (XML) mot den server som ursprungligen ställde förfrågan till att starta en analys. XML svaret innehåller både tekniska dataparametrar kring kundens uppkoppling samt ett analyssvar baserat på dessa tekniska parametrar. Utförligheten i svaret på en utförd analys varierar en aning beroende på switchtypen kunden sitter uppkopplad mot. Switchar av äldre hårdvarutyper presenterar generellt sett mindre kundportsdata jämfört med modernare varianter. Mindre kundportsdata leder till sämre utförlighet i analyssvaret. Därför lämpar sig detta analysverktyg bättre mot de modernare switcharna som finns i Telias nät. / A tool for analyzing the status of Fiber to the X (FTTX) customers in Telia’s network has been programmed in the Python programming language. The system consists of a module divided structure where analysis functions of similar types are bundled into module files. The system is designed to be easily further developed by adding more analysis modules in future projects. To perform an analysis on a specific customer, the system retrieves technical data parameters from the switch which the customer is connected to, and compares these parameters against predetermined values to find deviations. Simple Network Management Protocol (SNMP) and Telnet are the primary protocols used to retrieve data. Hypertext Transfer Protocol (HTTP) is used to transfer data as system input and output. The result of an analysis is sent as Extensible Markup Language (XML) back to the server that originally requested the start of an analysis. The XML reply contains technical data parameters describing the customer’s connection status and an analytical response based on these technical parameters. The amount of data presented in the XML response varies slightly depending on the type of switch the customer is connected to. Switches of older hardware types generally presents less customer port data compared to more modern switches. Less customer port data leads to poor detail in the analytical response, and therefore, this analysis tool is better suited to the modern switches found in Telia's network.

A melhora da confiabilidade em redes de distribuição de energia elétrica é um tema importante para as indústrias de fornecimento de eletricidade, devido aos regulamentos estritos em muitos países. Depois de uma falha na rede, algumas chaves são usadas para isolar a falha, enquanto outras restauram a energia a alguns consumidores. A ótima seleção das chaves que serão abertas ou fechadas para restaurar a energia é conhecido como o problema de restauração de serviço. A instalação de chaves em posições estratégicas pode reduzir o tempo de parada, e assim melhorar a confiabilidade da rede. A seleção ótima de posições para instalar chaves é conhecido como o problema de alocação de chaves. Estes dois problemas estão relacionados estreitamente. Esta dissertação estuda o problema de alocação de chaves, considerando o problema de restauração de serviço como um subproblema. Dois métodos são propostos para estimar a confiabilidade de uma rede de distribuição com um conjunto dado de chaves instaladas. O foco principal está nas heurísticas para resolver o problema composto. Propõe-se aqui métodos como busca tabu, procedimento de busca gulosa adaptativa aleatória (sigla em inglês: GRASP), e procedimento iterativo de construção por amostras com reconexão de caminhos. Também estuda-se o benefício dos métodos de construção gulosa, semigulosa, aleatória e por amostras, e estuda-se o desempenho das estratégias de busca local por amostras, primeira melhoria e melhor melhoria. Os diferentes métodos são comparados e analisados. Os resultados mostram que os métodos por amostras são baratos e levam a soluções de boa qualidade. O procedimento iterativo de construção por amostras com reconexão de caminhos é o melhor método proposto para resolver o problema composto que é proposto nesta dissertação. / The improvement of reliability in electrical power distribution networks is an important issue for electricity supply industries, due to strict regulations in many countries. After a failure in the network, some switches are used to isolate the failure, while others restore the energy to some consumers. The optimal selection of the switches to open or close to restore energy is called the service restoration problem. The installation of switches in strategic places may reduce the outage time in case of blackouts, and thus improve the reliability of the network. The optimal selection of places to install switches is called the switch allocation problem. These two problems are closely related. This dissertation studies the switch allocation problem, considering the service restoration problem as a sub-problem. Two methods are proposed to estimate the reliability of a distribution network with a given set of installed switches. The main focus is in heuristics to solve the joint problem. It proposes methods like tabu search, greedy randomized adaptive search procedure, and iterated sample construction with path relinking. It also studies the benefit of greedy, semigreedy, random, and sample construction methods, and studies the performance of sample, first improvement and best improvement local search strategies. The different methods are compared and analyzed. The results show that sample approaches are inexpensive and lead to solutions of good quality. Iterated sample construction with path relinking is the best method to solve the joint problem that is proposed in this dissertation.

abstract: Two major challenges in the transformer-less, single-phase PV string inverters are common mode leakage currents and double-line-frequency power decoupling. In the proposed doubly-grounded inverter topology with innovative active-power-decoupling approach, both of these issues are simultaneously addressed. The topology allows the PV negative terminal to be directly connected to the neutral, thereby eliminating the common-mode ground-currents. The decoupling capacitance requirement is minimized by a dynamically-variable dc-link with large voltage swing, allowing an all-film-capacitor implementation. Furthermore, the use of wide-bandgap devices enables the converter operation at higher switching frequency, resulting in smaller magnetic components. The operating principles, design and optimization, and control methods are explained in detail, and compared with other transformer-less, active-decoupling topologies. A 3 kVA, 100 kHz single-phase hardware prototype at 400 V dc nominal input and 240 V ac output has been developed using SiC MOSFETs with only 45 μF/1100 V dc-link capacitance. The proposed doubly-grounded topology is then extended for split-phase PV inverter application which results in significant reduction in both the peak and RMS values of the boost stage inductor current and allows for easy design of zero voltage transition. A topological enhancement involving T-type dc-ac stage is also developed which takes advantage of the three-level switching states with reduced voltage stress on the main switches, lower switching loss and almost halved inductor current ripple. In addition, this thesis also proposed two new schemes to improve the efficiency of conventional H-bridge inverter topology. The first scheme is to add an auxiliary zero-voltage-transition (ZVT) circuit to realize zero-voltage-switching (ZVS) for all the main switches and inherent zero-current-switching (ZCS) for the auxiliary switches. The advantages include the provision to implement zero state modulation schemes to decrease the inductor current THD, naturally adaptive auxiliary inductor current and elimination of need for large balancing capacitors. The second proposed scheme improves the system efficiency while still meeting a given THD requirement by implementing variable instantaneous switching frequency within a line frequency cycle. This scheme aims at minimizing the combined switching loss and inductor core loss by including different characteristics of the losses relative to the instantaneous switching frequency in the optimization process. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017