International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, Nevada / An innovative digital approach to analog noise synthesis is described. This method can be used to test bit synchronizers and other communications equipment over a wide range of data rates. A generator has been built which has a constant RMS output voltage and a well-defined, closely Gaussian amplitude distribution. Its frequency spectrum is flat within 0.3 dB from dc to an upper limit which can be varied from 1 Hz to over 100 MHz. Both simulation and practical measurement have confirmed that this generator can verify the performance of bit synchronizers with respect to the standard error rate curve.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / In this paper, a method for digital correlation detector that takes advantage of the frame-synchronization-pattern feature of coincidence rate and adopts a multiple-bit detection window is proposed. Based on this method, a new digital correlation detector with a neural network is designed. It can recognizes frame-synchronization-pattern with error bits and slippage bits correctly, which has been approved practically according to the experimental results.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / With the development of microelectronics and computer technology, telemetry computer systems are demanded to provide larger storage capacity and higher storage data rate than ever before. This paper fully considers various factors of a high-speed PCM fiber-optic telemetry system such as data format, data rate, data storage, the width of data storage, storage data rate. All these considerations lead to a new scheme with a semiconductor RAM and a dedicated program as its basic idea. This scheme chooses 1Mbits or 4Mbits static-RAM chips to implement the telemetry data storage device with a total capacity of 4Mbytes, 16Mbytes, or 64Mbytes. The software running on COMPAQ 386/25M or its compatibles is written in Turbo C 2. 0 to fetch, decompose, display and process data stored in the large-capacity RAM. The main task of the system processing software is to identify the flag words of frame sync-code -pattern and then demultiplex the data into separate channel data to be stored in the disk. Besides the ability to recognize specific data format, the software can also rectify data confusion to some extent. The scheme has already been proved to be efficient to receive large capacity of data with features of high data rate, high data storage in a short time.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes a Multi-Function Telemetry Input Module (TIM). The TIM module includes a 30 Mbps PCM frame synchronizer, a time code translator/generator, a PCM simulator and a tunable bit synchronizer all on a single PCI card. The module uses a generic architecture including: high density Field Programmable Gate Arrays (FPGAs), look-up table memory, dual port A/B data buffer memory and a full function PCI interface. The FPGA and the logic function of the card are downloadable via the PCI interface. This allows a single module to support many hardware functions in a telemetry front-end. The TIM is an integral part of a PC-based Advanced Telemetry Processing and Display System. This concept for hardware design ushers in a new generation of flexible downloadable telemetry products.

Στην παρούσα διπλωματική εργασία παρουσιάζεται η υλοποίηση του συγχρονισμού ενός δορυφορικού δέκτη τεχνολογίας DVB-S2 με χρήση προϊόντων από την βιβλιοθήκη Xilinx του Simulink της Matllab. Αρχικά εξετάσαμε τη γενική συμπεριφορά ενός δέκτη και στη συνέχεια κατανοώντας τα ιδιαίτερα χαρακτηριστικά της τεχνολογίας DVB-S2, πραγματοποιήσαμε θεωρητική μελέτη του κυκλώματος που θα υλοποιήσουμε. Σαν επέκταση της παραπάνω μελέτης εξηγήσαμε δίνοντας παραδείγματα, για ποιους λόγους σε κάθε σημείο του συγχρονιστή επελέχθη το εκάστοτε υλισμικό-λογισμικό, από θεωρητικής άποψης. Έπειτα μας δόθηκε ένα μοντέλο, το οποίο ήταν υλοποιημένο με προϊόντα από την γενική βιβλιοθήκη (Simulink) της Matllab· στη συνέχεια δημιουργήσαμε ύστερα από διεξοδικά πειράματα και συγκρίσεις ένα μοντέλο, υλοποιημένο με προϊόντα από τη βιβλιοθήκη Xilinx του Simulink της Matllab, με συμπεριφορά ίδια με αυτή του μοντέλου που μας δόθηκε. Τέλος, παρουσιάσαμε μέσω γραφικών παραστάσεων και γραφημάτων τόσο τη σύγκριση της συμπεριφοράς των δυο μοντέλων, όσο και τη λειτουργία και τις ιδιαιτερότητες αυτού καθ’ εαυτού του μοντέλου που δημιουργήσαμε. / In this diplomatic work we present the concretization of timing of satellite receptor of technology DVB-S2 with use of products from the library Xilinx of Simulink of Matlab. Initially we examined the general behavior of receptor and afterwards comprehending the particular characteristics of technology DVB-S2, we realized theoretical study of circuit that we will materialize. As extension of previous study we explained giving examples, for what reasons we chose each hardware-software, from theoretical point of view. Then we were given a model, which was materialized with products from the general library (Simulink) of Matllab; afterwards we created after extensive experiments and comparisons, a model, materialized with products from the library Xilinx of Matllab Simulink, with behavior precisely same with that of model that was given to us. Finally, we presented via graphic representations and illustrations both the comparison of behavior of two models, and the operation and the particularities each one of the models we created.

No description available.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes the new Telemetry Processor Hardware (TPH) that Avtec Systems has developed for the Deep Space Network (DSN) Telemetry Processor (TLP) system. Avtec is providing the Telemetry Processor Hardware to RTLogic! for integration into the Telemetry Processor system. The Deep Space Network (DSN) is an international network of antennas that supports interplanetary spacecraft missions for exploration of the solar system and the universe. The Jet Propulsion Laboratory manages the DSN for NASA. The TLP system provides the capability to acquire, process, decode and distribute deep space probe and Earth orbiter telemetry data. The new TLP systems will be deployed at each of the three deep-space communications facilities placed approximately 120 degrees apart around the world: at Goldstone, California; near Madrid, Spain; and near Canberra, Australia. The Telemetry Processor Hardware (TPH) supports both CCSDS and TDM telemetry data formats. The TPH performs the following processing steps: soft-symbol input selection and measurement; convolutional decoding; routing to external decoders; time tagging; frame synchronization; derandomization; and Reed-Solomon decoding. The TPH consists of a VME Viterbi Decoder/MCD III Interface board (VM-7001) and a PCI-mezzanine Frame Synchronizer/Reed-Solomon Decoder (PMC- 6130-J) board. The new Telemetry Processor Hardware is implemented using the latest Field Programmable Gate Array (FPGA) technology to provide the density and speed to meet the current requirements as well as the flexibility to accommodate processing enhancements in the future.

<p><p>The Dual Clutch Transmission (DCT) is a relatively new kind of transmission which shows increased efficiency and comfort compared to manual transmissions. Its construction is much like two parallell manual transmissions, where the gearshifts are controlled automatically. The gear-shift of a manual transmission involves a synchronization process, which synchronizes and locks the input shaft to the output shaft via the desired gear ratio. This process, which means transportation of a synchronizer sleeve, is performed by moving the gear shift lever which is connected to the sleeve. In a DCT, there is no mechanical connection between the gear-shift lever and the sleeve. Hence, an actuator system, controlled by a control system, must be used.</p><p>This report includes modelling, control system design and simulation results of a DCT synchronization process. The thesis work is performed at GM Powertrain (GMPT) in Trollhättan. At the time of this thesis, there is no DCT produced by GM, and therefore the results and conclusions rely on simulations. Most of the used system parameters are reasonable values collected from employees at GMPT and manual transmission literature.</p><p>The focus of the control design is to achieve a smooth, rather than fast, movement of the synchronizer sleeve. Simulations show that a synchronization process can be performed in less than 400 ms under normal conditions. The biggest problems controlling the sleeve position occur if there is a large amount of drag torque affecting the input shaft. Delay problems also worsen the performance a lot. An attempt to predict the synchronizer sleeve position is made and simulations shows advantages of that.</p><p>Some further work is needed before the developed control software can be used on a real DCT. Investigations of sensor noise robustness and the impact of dogging forces are the most important issues to be further investigated. Implementation of additional functionality for handling special conditions are also needed.</p></p>

The Dual Clutch Transmission (DCT) is a relatively new kind of transmission which shows increased efficiency and comfort compared to manual transmissions. Its construction is much like two parallell manual transmissions, where the gearshifts are controlled automatically. The gear-shift of a manual transmission involves a synchronization process, which synchronizes and locks the input shaft to the output shaft via the desired gear ratio. This process, which means transportation of a synchronizer sleeve, is performed by moving the gear shift lever which is connected to the sleeve. In a DCT, there is no mechanical connection between the gear-shift lever and the sleeve. Hence, an actuator system, controlled by a control system, must be used. This report includes modelling, control system design and simulation results of a DCT synchronization process. The thesis work is performed at GM Powertrain (GMPT) in Trollhättan. At the time of this thesis, there is no DCT produced by GM, and therefore the results and conclusions rely on simulations. Most of the used system parameters are reasonable values collected from employees at GMPT and manual transmission literature. The focus of the control design is to achieve a smooth, rather than fast, movement of the synchronizer sleeve. Simulations show that a synchronization process can be performed in less than 400 ms under normal conditions. The biggest problems controlling the sleeve position occur if there is a large amount of drag torque affecting the input shaft. Delay problems also worsen the performance a lot. An attempt to predict the synchronizer sleeve position is made and simulations shows advantages of that. Some further work is needed before the developed control software can be used on a real DCT. Investigations of sensor noise robustness and the impact of dogging forces are the most important issues to be further investigated. Implementation of additional functionality for handling special conditions are also needed.

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers.