Αντικείμενο της διατριβής είναι η επίδειξη μεθόδων, που βρίσκουν εφαρμογή, τόσο ειδικότερα στην σχεδίαση πολύπλοκων ψηφιακών μικροηλεκτρονικών κυκλωμάτων μεγάλης ταχύτητας, για τηλεπικοινωνιακά δίκτυα οπτικών ινών, όσο και γενικότερα για την επίλυση θεμάτων χρονισμού, που προκύπτουν κατά την υλοποίηση πολύπλοκων ολοκληρωμένων συστημάτων πάνω σε chip. Όσον αφορά, τον χώρο των τηλεπικοινωνιακών κυκλωμάτων, παρουσιάζονται μέθοδοι, τόσο για την συνολική οργάνωση του ολοκληρωμένου κυκλώματος, όσο και για την κυκλωματική υλοποίηση λειτουργικών μονάδων κοινών σε τηλεπικοινωνιακά κυκλώματα, με απαιτήσεις υψηλής ταχύτητας, χαμηλής κατανάλωσης, και ταυτόχρονης συνύπαρξης πολλαπλών ρολογιών. Η επίδειξη των προτεινόμενων μεθόδων καθώς και η επαλήθευση της ορθότητά τους, πραγματοποιείται, μέσα από την υλοποίηση σε πυρίτιο, ενός πολύπλοκου τηλεπικοινωνιακού ολοκληρωμένου κυκλώματος, με υψηλές απαιτήσεις ταχύτητας λειτουργίας. Όσον αφορά, τον γενικότερο χώρο της σχεδίασης πολύπλοκων ολοκληρωμένων System-on-Chip (SoC), παρουσιάζονται μέθοδοι για την επίλυση προβλημάτων χρονισμού, στα σύγχρονα ψηφιακά ολοκληρωμένα κυκλώματα, που σχετίζονται με την διάδοση και τον πολλαπλασιασμό της συχνότητας του ρολογιού, στο εσωτερικό των κυκλωμάτων αυτών. Πιο συγκεκριμένα, παρουσιάζονται μέθοδοι που μπορούν να εφαρμοστούν, τόσο για την εξάλειψη της παρέκκλισης, μεταξύ των κόμβων των εσωτερικών ρολογιών, όσο και για την εξάλειψη της παρέκκλισης μεταξύ εξωτερικού και εσωτερικού ρολογιού, στα ολοκληρωμένα κυκλώματα. Όσον αφορά το δεύτερο, η συχνότητα του εσωτερικού ρολογιού δεν ταυτίζεται απαραίτητα με αυτήν του εξωτερικού, αλλά επιτρέπεται να έχει πολλαπλάσια τιμή από αυτήν. Για την ευθυγράμμιση του εσωτερικού με το εξωτερικό ρολόι, προτείνεται η συστηματική μέθοδος LCD-SMD, η οποία είναι κατάλληλη για χρήση σε ολοκληρωμένα όπου επικρατούν συνθήκες μακρύ οδηγού ρολογιού, παράγει εσωτερικό ρολόι πολλαπλάσιο του εξωτερικού με σταθερό 50% duty-cycle, έχει μικρό χρόνο κλειδώματος, και χρησιμοποιεί εξ’ ολοκλήρου ψηφιακές λογικές πύλες. Η επικύρωση της ορθότητας των προτεινόμενων μεθόδων για θέματα χρονισμού, γίνεται κατά ένα μέρος με υλοποίηση σε πυρίτιο, και κατά ένα άλλο μέρος με εξομοιώσεις. / This Thesis aims to demonstrate design methods that can be applied as much in the design of high complexity, high speed, digital integrated circuits for optical fiber networks, as more generally to resolve timing issues, arising during the implementation of integrated circuits (IC’s). Specifically, in this Thesis we present methods for the holistic organization of a digital integrated circuit (driven by the needs imposed by nowadays telecommunications area), as well as methods regarding circuit implementation of various common functional units in telecommunications circuits that require high speed, low power and multiple clocks. The proposed methods are demonstrated and validated through the silicon implementation of a complex telecom integrated circuit (SDH framer). The design of the here-above mentioned chips lie into the more general area of the complex integrated Systems-on-Chips (SoCs). The methods developed in the Thesis, concern the distribution and frequency multiplication of the clock signal, inside the chip. In particular, we address between others, methods to remove the skew between the internal clock nodes, as well as methods to remove the skew between the internal and external clock. The internal clock frequency is allowed to be a multiple of the external clock frequency. For the alignment of the internal with the external clock, the systematic open-loop method LCD-SMD has been proposed, which is applicable to IC’s with long clock driver conditions. Through this method, we accomplish the generation of an internal clock with multiple frequencies than the external, while preserving a constant 50% duty-cycle. The method results into a fast lock time, and employs only standard digital logic gates. The proposed methods are validated both by silicon implementation and by simulations.

Nous proposons une méthode supervisée de détection de chutes de personnes en temps réel, robusteaux changements de point de vue et d'environnement. La première partie consiste à rendredisponible en ligne une base de vidéos DSFD enregistrées dans quatre lieux différents et qui comporteun grand nombre d'annotations manuelles propices aux comparaisons de méthodes. Nousavons aussi défini une métrique d'évaluation qui permet d'évaluer la méthode en s'adaptant à la naturedu flux vidéo et la durée d'une chute, et en tenant compte des contraintes temps réel. Dans unsecond temps, nous avons procédé à la construction et l'évaluation des descripteurs spatio-temporelsSTHF, calculés à partir des attributs géométriques de la forme en mouvement dans la scène ainsique leurs transformations, pour définir le descripteur optimisé de chute après une méthode de sélectiond'attributs. La robustesse aux changements d'environnement a été évaluée en utilisant les SVMet le Boosting. On parvient à améliorer les performances par la mise à jour de l'apprentissage parl'intégration des vidéos sans chutes enregistrées dans l'environnement définitif. Enfin, nous avonsréalisé, une implantation de ce détecteur sur un système embarqué assimilable à une caméra intelligentebasée sur un composant SoC de type Zynq. Une démarche de type Adéquation AlgorithmeArchitecture a permis d'obtenir un bon compromis performance de classification/temps de traitement

This thesis aims to define software and hardware mechanisms helping in the management the Heterogeneous and dynamically Reconfigurable Systems-on-Chip (HRSoC). The heterogeneity is due to the presence of general processing units and reconfigurable IPs. Our objective is to provide to an application developer an abstracted view of this heterogeneity, regarding the task mapping on the available processing elements. First, we homogenize the user interface defining a hardware thread model. Then, we pursue with the homogenization of the hardware threads management. We implemented OS services permitting to save and restore a hardware thread context. Conception tools have also been developed in order to overcome the relocation issue. The last step consisted in extending the access to the distributed OS services to every thread running on the platform. This access is provided independently from the thread location and is is realized implementing the MRAPI API. With these three steps, we build a solid basis to, in future work, provide to the developer, a conception flow dedicated to HRSoC allowing to perform precise architectural space explorations. Finally, to validate these mechanisms, we realize a demonstration platform on a Virtex 5 FPGA running a dynamic tracking application.

Made available in DSpace on 2014-12-17T15:47:45Z (GMT). No. of bitstreams: 1 SilvioRFA.pdf: 3522539 bytes, checksum: 0e7ac6eda46a29d5f5968d779986fb03 (MD5) Previous issue date: 2008-04-11 / The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform / O aumento na capacidade de integra??o de transistores permitiu o desenvolvimento de sistemas completos, com in?meros componentes, dentro de um ?nico chip, s?o os chamados SoCs (System-on-Chip). No entanto, o subsistema de interconex?o utilizado pode limitar a escalabilidade dos SoCs, como os barramentos, ou ser uma solu??o ad hoc, como a hierarquia de barramentos. Desse modo, a solu??o ideal para interconex?o no SoCs s?o as redes em chip ou NoCs (Network-on-Chip). As NoCs permitem m?ltiplas conex?o ponto-a-ponto entre os componente e podem ser reusadas em projetos diversos. Entretanto, o uso de NoCs pode representar o aumento na complexidade do projeto do sistema, da ?rea em chip e/ou pot?ncia dissipada. Dessa forma, ? necess?rio ampliar o horizonte de utiliza??o dos sistemas ou quebrar o paradigma do seu desenvolvimento. Assim, ? proposto um sistema baseado em uma NoC, onde as aplica??es s?o descritas em forma de pacotes e executadas de roteador em roteador durante o percurso entre origem e destino dos pacotes, sem a necessidade do uso de processadores convencionais. Para permitir a execu??o de aplica??es, independente do n?mero de instru??es e das dimens?es da rede, foi desenvolvido o algoritmo spiral complement, que permite re-rotear pacotes at? que todas as instru??es contidas nele sejam executadas. Portanto, o objetivo desse trabalho foi estudar a viabilidade do desenvolvimento de tal sistema, denominado sistema IPNoSys. Nesse estudo, foi desenvolvida em SystemC, com precis?o de ciclo, uma ferramenta para simula??o do sistema, a qual permite executar aplica??es implementadas na linguagem de descri??o de pacotes, tamb?m desenvolvida para esse fim. Atrav?s da ferramenta podem ser obtidos diversos resultados que permitem avaliar o funcionamento e desempenho do sistema. A metodologia empregada para descri??o das aplica??es corresponde, a priori, em obter o grafo de fluxo de dados da aplica??o em alto n?vel, e desse grafo descrev?-la em um ou mais pacotes. Utilizando essa metodologia, foram realizados tr?s estudos de casos: contador, DCT-2D e adi??o de ponto flutuante. O contador foi usado para avaliar a capacidade do sistema em tratar situa??es de deadlock e executar aplica??es em paralelo. A DCT-2D foi utilizada para realizar compara??es com a plataforma STORM. E, finalmente, a adi??o de ponto flutuante teve como objetivo ser usada como rotina de tratamento de uma instru??o n?o implementada em hardware. Os resultados de simula??o apontam favoravelmente com rela??o ? viabilidade do desenvolvimento do sistema IPNoSys. Mostrando que ? poss?vel executar aplica??es em forma de pacotes, inclusive paralelamente, sem interrup??es provocadas por eventuais deadlocks, e ainda indicam maior efici?ncia do sistema IPNoSys a respeito do tempo de execu??o comparada a plataforma STORM

Made available in DSpace on 2014-12-17T15:47:50Z (GMT). No. of bitstreams: 1 BrunoCO.pdf: 708202 bytes, checksum: 3eb4368a0c268064bcd6ad892e1f2c0c (MD5) Previous issue date: 2009-05-22 / The constant increase of complexity in computer applications demands the development of more powerful hardware support for them. With processor's operational frequency reaching its limit, the most viable solution is the use of parallelism. Based on parallelism techniques and the progressive growth in the capacity of transistors integration in a single chip is the concept of MPSoCs (Multi-Processor System-on-Chip). MPSoCs will eventually become a cheaper and faster alternative to supercomputers and clusters, and applications developed for these high performance systems will migrate to computers equipped with MP-SoCs containing dozens to hundreds of computation cores. In particular, applications in the area of oil and natural gas exploration are also characterized by the high processing capacity required and would benefit greatly from these high performance systems. This work intends to evaluate a traditional and complex application of the oil and gas industry known as reservoir simulation, developing a solution with integrated computational systems in a single chip, with hundreds of functional unities. For this, as the STORM (MPSoC Directory-Based Platform) platform already has a shared memory model, a new distributed memory model were developed. Also a message passing library has been developed folowing MPI standard / O constante aumento da complexidade das aplica??es demanda um suporte de hardware computacionalmente mais poderoso. Com a aproxima??o do limite de velocidade dos processadores, a solu??o mais vi?vel ? o paralelismo. Baseado nisso e na crescente capacidade de integra??o de transistores em um ?nico chip surgiram os chamados MPSoCs (Multiprocessor System-on-Chip) que dever?o ser, em um futuro pr?ximo, uma alternativa mais r?pida e mais barata aos supercomputadores e clusters. Aplica??es tidas como destinadas exclusivamente a execu??o nesses sistemas de alto desempenho dever?o migrar para m?quinas equipadas com MPSoCs dotados de dezenas a centenas de n?cleos computacionais. Aplica??es na ?rea de explora??o de petr?leo e g?s natural tamb?m se caracterizam pela enorme capacidade de processamento requerida e dever?o se beneficiar desses novos sistemas de alto desempenho. Esse trabalho apresenta uma avalia??o de uma tradicional e complexa aplica??o da ind?stria de petr?leo e g?s natural, a simula??o de reservat?rios, sob a nova ?tica do desenvolvimento de sistemas computacionais integrados em um ?nico chip, dotados de dezenas a centenas de unidades funcionais. Para isso, um modelo de mem?ria distribu?da foi desenvolvido para a plataforma STORM (MPSoC Directory-Based Platform), que j? contava com um modelo de mem?ria compartilhada. Foi desenvolvida, ainda, uma biblioteca de troca de mensagens para esse modelo de mem?ria seguindo o padr?o MPI

Les systèmes parallèles de type multi/pluri-cœurs permettant d'obtenir une grande puissance de calcul à bas coût énergétique sont de nos jours une réalité. Néanmoins, l'exploitation des performances de ces architectures dépend de l'efficacité du système à gérer les accès aux données. Le but de nos travaux est d'améliorer l'efficacité de ces accès en exploitant les caractéristiques de l'architecture matérielle.Dans une première partie, nous proposons une nouvelle organisation de la hiérarchie des mémoires caches qui maximise l'utilisation de l'espace de stockage disponible à chaque niveau. Cette solution, basée sur les architectures à accès non uniforme au cache (NUCA), supporte les transferts inter et intra-niveau de la hiérarchie. Elle requiert un protocole de cohérence de cache qui s'adapte à ses spécifications.Certes, le transfert des données au niveau de la hiérarchie est aussi un déterminant de la performance du système. Dans une seconde partie, nous prenons en compte les besoins de communication spécifiques du protocole. Nous proposons un réseau virtualisé comme support de communication ad-hoc afin de gérer le trafic de cohérence à moindre coût. Ce dernier relie les caches d'un même niveau pour supporter les transferts intra-niveaux, qui sont une spécificité de notre protocole, en vue de réduire la latence moyenne d'accès. / Multi/many-cores parallel systems for high-power computing at low energy costs are nowadays a reality. However, exploiting the performance of these architectures depends on the efficiency of the system in managing data accesses. The aim of our work is to improve the efficiency of these accesses by exploiting the hardware architecture characteristics.In a first part, we propose a new cache hierarchy organization that aims at maximizing the use of the available storage space at each level. This solution, based on non-uniform cache access architectures (NUCA), supports inter and intra-level transfers of the hierarchy. It requires a cache coherency protocol that suits its specifications.Obviously, the transfer of data in the hierarchy is also a determinant of the system performance. In a second part, we consider the specific communication needs of the protocol. We suggest the use of a virtualized network as an ad-hoc communication medium to manage consistency traffic at a lower cost. It links the caches of the same level to support intra-level transfers, which are a specificity of our protocol, in order to reduce the average access latency.

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.

La conception des systèmes de contrôle embarqués devient de plus en plus complexe en raison des algorithmes utilisés, de l'augmentation des besoins industriels et de la nature des domaines d'applications. Une façon de gérer cette complexité est de concevoir les contrôleurs correspondant en se basant sur des plateformes numériques puissantes et ouvertes. Plus précisément, cette thèse s'intéresse à l'utilisation des plateformes FPGA System-on-Chip (SoC) pour la mise en œuvre des algorithmes d'entraînement électrique pour des applications avioniques. Ces dernières sont caractérisées par des difficultés techniques telles que leur environnement de travail (pression, température élevée) et les exigences de performance (le haut degré d'intégration, la flexibilité). Durant cette thèse, l'auteur a contribué à concevoir et à tester un contrôleur numérique pour un variateur de vitesse synchrone qui doit fonctionner à 200 °C de température ambiante. Il s'agit d'une commande par flux orienté (FOC) pour une Machine Synchrone à Aimants Permanents (MSAP) associée à un capteur de type résolveur. Une méthode de conception et de validation a été proposée et testée en utilisant une carte FPGA ProAsicPlus de la société Actel/Microsemi. L'impact de la température sur la fréquence de fonctionnement a également été analysé. Un état de l'art des technologies basées sur les SoC sur FPGA a été également présenté. Une description détaillée des plateformes numériques récentes et les contraintes en lien avec les applications embarquées a été également fourni. Ainsi, l'intérêt d'une approche basée sur SoC pour des applications d'entrainements électriques a été démontré. D'un autre coté et pour profiter pleinement des avantages offertes par les SoC, une méthodologie de Co-conception matériel-logiciel (hardware-software (HW-SW)) pour le contrôle d'entraînement électrique a été proposée. Cette méthode couvre l'ensemble des étapes de développement de l'application de contrôle à partir des spécifications jusqu'à la validation expérimentale. Une des principales étapes de cette méthode est le partitionnement HW-SW. Le but est de trouver une combinaison optimale entre les modules à mettre en œuvre dans la partie logiciel et celles qui doivent être mis en œuvre dans la partie matériel. Ce problème d'optimisation multi-objectif a été réalisé en utilisant l'algorithme de génétique, Non-Dominated Sorting Genetic Algorithm (NSGA-II). Ainsi, un Front de Pareto des solutions optimales peut être déduit. L'illustration de la méthodologie proposée a été effectuée en se basant sur l'exemple du régulateur de vitesse sans capteur utilisant le filtre de Kalman étendu (EKF). Le choix de cet exemple correspond à une tendance majeure dans le domaine des contrôleurs embraqués pour entrainements électriques. Par ailleurs, la gestion de l'architecture du contrôleur embarqué basée sur une approche SoC a été effectuée en utilisant un système d'exploitation temps réel. Afin d'accélérer les services de ce système d'exploitation, une unité temps réel a été développée en VHDL et associée au système d'exploitation. Il s'agit de placer les services d'ordonnanceur et des processus de communication du système d'exploitation logiciel au matériel. Ceci a permis une accélération significative du traitement. La validation expérimentale d'un contrôleur du courant a été effectuée en utilisant un banc de test du laboratoire. Les résultats obtenus prouvent l'intérêt de l'approche proposée. / Designing embedded control systems becomes increasingly complex due to the growing of algorithm complexity, the rising of industrials requirements and the nature of application domains. One way to handle with this complexity is to design the corresponding controllers on performing powerful and open digital platforms. More specifically, this PhD deals with the use of FPGA System-on-Chip (SoC) platforms for the implementation of complex AC drive controllers for avionic applications. These latters are characterized by stringent technical issues such as environment conditions (pressure, high temperature) and high performance requirements (high integration, flexibility and efficiency). During this thesis, the author has contributed to design and to test a digital controller for a high temperature synchronous drive that must operate at 200°C ambient. It consists on the Flux Oriented Controller (FOC) for a Permanent Magnet Synchronous Machine (PMSM) associated with a Resolver sensor. A design and validation method has been proposed and tested using a FPGA ProAsicPlus board from Actel-Microsemi Company. The impact of the temperature on the operating frequency has been also analyzed. A state of the art FPGA SoC technology has been also presented. A detailed description of the recent digital platforms and constraints in link with embedded applications was investigated. Thus, the interest of a SoC-based approach for AC drives applications was also established. Additionally and to have full advantages of a SoC based approach, an appropriate HW-SW Co-design methodology for electrical AC drive has been proposed. This method covers the whole development steps of the control application from the specifications to the final experimental validation. One of the main important steps of this method is the HW-SW partitioning. The goal is to find an optimal combination between modules to be implemented in software and those to be implemented in hardware. This multi-objective optimization problem was performed with the Non-Dominated Sorting Genetic Algorithm (NSGA-II). Thus, the Pareto-Front of optimal solution can be deduced. The illustration of the proposed Co-design methodology was made based on the sensorless speed controller using the Extended Kalman Filter (EKF). The choice of this benchmark corresponds to a major trend in embedded control of AC drives. Besides, the management of SoC-based architecture of the embedded controller was allowed using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration has been achieved. The experimentation tests based on digital current controller were also carried out using a laboratory set-up. The obtained results prove the interest of the proposed approach.