Processor design has evolved over the years to take advantage of new technology and innovative concepts in order to improve performance. Diminishing returns for improvements based on current techniques such as exploiting instruction-level parallelism have caused designers to shift their focus. Rather then focusing on single-threaded architectures, designers have increasingly sought to improve system performance and increase overall throughput by exploiting thread-level parallelism through multithreaded multi-core architectures. Software modeling and simulation are common techniques used to aid hardware design. Through simulation, different architectures can be explored and verified before hardware is actually built. An appropriate choice for the level of abstraction can reduce the complexity and the time required to create and simulate software models. The first contribution of this thesis is a transaction-level simulation model of a multithreaded multi-core processor. The transaction level is a high level of abstraction that hides computational details from the designer allowing key architectural elements to be quickly explored. The processor model that has been implemented for this thesis is flexible and can be used to explore various designs by simulating different processor and cache configurations. The processor model is written in SystemC, which is a standard design and verification language that is built on C++ and that can be used to model hardware systems. The second contribution of this thesis is the development of an application model that seeks to characterize the behavior of instruction execution and data accesses in a program. An application's instruction trace can be profiled to produce a model that can be used to generate a synthetic trace with similar characteristics. The synthetic trace can then be used in place of large trace files to drive the SystemC-based processor model. The application model can also produce various workload scenarios for multiprocessor simulation. From experimentation, various processor configurations and different workload scenarios were simulated to explore the potential benefits of a multi-core multithreaded processor architecture. Performance increased with diminishing returns with additional multi-core multithreading support. However, these improvement were limited by the utilization of the shared bus. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-08-09 11:45:46.749

In order to improve the performance of simulation and the convenience of use with OSCI TLM-2.0 Standard on QEMU and SystemC based virtual platform we proposed previously called QSC, this thesis presents a novel approach for integrating OSCI TLM-2.0 with QSC. By moving the OSCI TLM-2.0 interconnect bus outside of the Bus Function Model (BFM), the proposed approach can not only accelerate the simulation speed but also make it easy to add OSCI TLM-2.0 based Intellectual Properties (IPs) to the QSC. Experimental results show that the proposed approach can speed up all the simulations by a factor from 2.8 up to 3.255 on average when compared with the previous approach.

Made available in DSpace on 2014-06-12T15:59:37Z (GMT). No. of bitstreams: 2 arquivo5344_1.pdf: 3740112 bytes, checksum: a4e42be0c5b4bb8e1fc9a30a86fbe8d8 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2006 / No competitivo mercado de sistemas digitais dedicados, a crescente demanda por produtos com funcionalidades cada vez mais complexas tem tornado o projeto de tais sistemas um grande desafio. Neste cenário, torna-se necessária à construção de modelos virtuais de sistemas, em diferentes níveis de abstração, a fim de permitir a exploração do espaço de projeto e a validação funcional dos mesmos, antes de implementações em plataformas alvo. SystemC é uma biblioteca de classes C++ que permite a modelagem e simulação de tais modelos e que tem conquistado espaço diante de gigantes do mercado. Ferramentas de desenvolvimento de sistemas tradicionalmente necessitam de mecanismos de introspecção para oferecer serviços de apoio. Introspecção é o ato de extrair informações a respeito de um dado programa ou componente de software. Contextos típicos que podem demonstrar a relevância da extração destas informações são os ambientes de composição de sistemas de apoio ao paradigma de projetos baseados em plataforma. Estes ambientes necessitam extrair informações estruturais e comportamentais de comunicação e sincronização, tanto da própria aplicação quanto da especificação da plataforma. As informações extraídas são de extrema utilidade para apoiar projestistas nas atividades de mapeamento entre os componentes do sistema. O projeto aqui proposto destinou-se ao desenvolvimento de técnicas para identificação de elementos estruturais e comportamentais a partir de sistemas especificados em SystemC. Uma vez identificados, estes elementos puderam então ter suas informações extraídas e disponibilizadas. Esta pesquisa resultou na construção de um mecanismo intitulado SCExamine que tem o objetivo de implementar as técnicas de introspecção propostas neste trabalho. O mecanismo de introspecção foi aplicado em vários modelos de sistemas, dentre eles o modelo de uma CPU RISC atualmente distribuída na biblioteca SystemC padrão. As informações extraídas são disponibilizadas por meio de arquivos XML que podem ser facilmente utilizadas por outras ferramentas de apoio ao desenvolvimento de sistemas. A obtenção de tais informações de maneira automatizada proporciona um aumento significativo na produtividade de projetistas que utilizam SystemC como linguagem de especificação de sistemas

With the increasing complexity of Application Specific Integrated Circuits (ASICs), System-On-a-Chip (SoC) design seems to be the current chip design paradigm. Unlike ASICs, SoCs are a potpourri of diverse components, including general-purpose or special-purpose processors. Designing and testing these designs require a new methodology that supports system level modeling and hardware-software co-design. The Hardware Description Languages (HDLs) available today cannot meet this challenge. SystemC is a new modeling language based on C++. Models written in SystemC are executable and do not dictate either hardware or software implementation. The model written in SystemC can be synthesized to hardware using the CoCentric SystemC Compiler (CCSC). Thus, the combination of SystemC and CCSC has the potential to be a powerful SoC design technique. This thesis examines the usefulness of SystemC and CCSC to model and synthesize a GSM system. The encoders and decoders used in the GSM system are complex and represent challenging problems in the real world. The modeling methodology using SystemC is considered and the synthesis issues with CCSC are detailed. Simulation results using real sound samples and synthesis results are presented. Areas for future work are then outlined. / Master of Science

Ce travail vise la modélisation au niveau système, en langage SystemC-AMS, et la simulation d'un émetteur-récepteur au standard Bluetooth Low Energy (BLE). L'objectif est d'analyser la relation entre les performances, en termes de BER et la consommation d'énergie du transceiver. Le temps de simulation d’un tel système, à partir de cas d’étude (use case) réaliste, est un facteur clé pour le développement d’une telle plateforme. De plus, afin d’obtenir des résultats de simulation le plus précis possible, les modèles « haut niveau » doivent être raffinés à partir de modèles plus bas niveau où de mesure. L'approche dite Meet-in-the-Middle, associée à la méthode de modélisation équivalente en Bande Base (BBE, BaseBand Equivalent), a été choisie pour atteindre les deux conditions requises, à savoir temps de simulation « faible » et précision des résultats. Une simulation globale d'un système de BLE est obtenue en intégrant le modèle de l'émetteur-récepteur dans une plateforme existante développée en SystemC-TLM. La simulation est basée sur un système de communication de deux dispositifs BLE, en utilisant différents scénarios (différents cas d'utilisation de BLE). Dans un premier temps nous avons modélisé et validé chaque bloc d’un transceiver BT. Devant le temps de simulation prohibitif, les blocs RF sont réécrits en utilisant la méthodologie BB, puis raffinés afin de prendre en compte les non-linéarités qui vont impacter le couple consommation, BER. Chaque circuit (chaque modèle) est vérifié séparément, puis une première simulation système (point à point entre un émetteur et un récepteur) est effectuée / This work aims at system-level modelling a defined transceiver for Bluetooth Low energy (BLE) system using SystemC-AMS. The goal is to analyze the relationship between the transceiver performance and the accurate energy consumption. This requires the transceiver model contains system-level simulation speed and the low-level design block power consumption and other RF specifications. The Meet-in-the-Middle approach and the Baseband Equivalent method are chosen to achieve the two requirements above. A global simulation of a complete BLE system is achieved by integrating the transceiver model into a SystemC-TLM described BLE system model which contains the higher-than-PHY levels. The simulation is based on a two BLE devices communication system and is run with different BLE use cases. The transceiver Bit-Error-Rate and the energy estimation are obtained at the end of the simulation. First, we modelled and validated each block of a BT transceiver. In front of the prohibitive simulation time, the RF blocks are rewritten by using the BBE methodology, and then refined in order to take into account the non-linearities, which are going to impact the couple consumption, BER. Each circuit (each model) is separately verified, and then a first BLE system simulation (point-to-point between a transmitter and a receiver) has been executed. Finally, the BER is finally estimated. This platform fulfills our expectations, the simulation time is suitable and the results have been validated with the circuit measurement offered by Riviera Waves Company. Finally, two versions of the same transceiver architecture are modelled, simulated and compared

The aim of this work is to investigate the possibility to implement a configurable NPU (Network Processing Unit) in the next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture). The NPU is constructed so that it can be configured for either Ethernet or xIO-s, as either a transmitter or a receiver. The motive for doing the work is that many protocols have similar functions and there could be possible advantages to have a configurable protocol choice in future hardware. A model of a NPU will be created in SystemC using the TLM 2.0 interface. The model will be analyzed to evaluate its complexity regarding a possible modification to also make it configurable for CPRI. The result that is presented is that it would be possible to implement a configurable NPU in the future EMCAs. The result is based on the conclusion that the protocols use many similar functions and most of the blocks could be made configurable for use with different protocols. Configurable blocks would benefit a configurable NPU as it would require fewer resources than separate blocks for each protocol.

Un dels avantatges d'usar plataformes virtuals o prototipat virtual enlloc del maquinari real pel desenvolupament de programari encastat és la capacitat d'alguns simuladors de fer captures del seu estat. Si el model del sistema complet és prou detallat, pot tardar uns quants minuts (inclús hores) per simular l'engegada d'un Sistema Operatiu. Si es pren una captura just després de que ha acabat d'engegar, cada cop que calgui corre el programari encastat, els dissenyadors poden simplement recuperar la captura i continuar-la. Recuperar una captura normalment porta pocs segons. Aquest guany es trasllada en una major productivitat, especialment quan es treballa amb sistemes encastat, amb programari complex sobre Sistemes Operatius com en els dispositius actuals. En aquesta tesi es presenta en primer lloc el treball realitzat per afegir un llenguatge de descripció de sistemes anomenat SystemC a dues plataformes virtuals diferents. Aquesta tasca es realitzà per una eina comercial i desprès es traslladà a una plataforma de codi obert. També es presenta una sèrie de modificacions al llenguatge SystemC per suportar la captura d'instantànies. Aquestes modificacions faran possible poder agafar l'estat de la simulació en SystemC i salvar-les al disc. Més tard, la simulació es pot recuperar en el mateix estat on es trobava, sense canvis en els seus components. Aquestes millores ajudaran al llenguatge SystemC a ser més àmpliament usat en el món de les Plataformes Virtuals. / One advantage of using a virtual platform or virtual prototype over real hardware for embedded software development and testing is the ability of some simulators to take checkpoints of their state. If the entire system model is detailed enough, it might take several minutes (or even hours) to simulate booting the O.S. If a snapshot of the simulation is saved just after it has finished booting, each time it is necessary to run the embedded software, designers can simply restore the snapshot and go. Restarting a checkpoint typically takes a few seconds. This can translate into a major productivity gain, especially when working with embedded system with complex SW stacks and O.S. like modern embedded devices. In this dissertation we present in firstly our work on adding a description level language as SystemC to two Virtual Platforms. This work was done for a commercial Virtual Platform, and later translated to a open-sourced Platform. This thesis also presents a set of modifications to SystemC language to support checkpointing. These modifications will make it possible to take the state of a SystemC running simulation and save it to disk. Later, the same simulation can be restored to the same point it was before, without any change to the simulated modules. These changes would help SystemC to be suitable for use by Virtual Platforms as a description language.

The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can explore the relation between hardware architecture and software operation, there will be a great help for designing SoC platform. This paper builds the highly abstract simulation platform by using the development tool of SystemC and Coware for 3D graphics SoC. SystemC is entirely based on C++, so that Coware Inc. supports many TLM IP modules (like ARM CPU, ARM BUS, Memory, and etc.) for designer. For the purpose of fast building and modifying module by designer, this paper discusses 1. the behavior module performance in 3D Graphics Traditional Architecture, Tile-based Architecture of non-pipeline, pipeline, and GE&DMA Concurrence. 2. If it can use the software application to control procedure order of GE and RE, it would decrease the read/write times for RE reading from Tile. 3. To modify the read/write mechanism of Tile Buffer and change the returned values from memory, it would reduce the read/write times from memory. 4. And we need to observe FIFO sizes of traditional architecture to estimate affection performance.5. It uses Tile-Divider to predict the cutting triangle. Finally, 6. it modifies the AHB bus to AXI bus and divides single memory; therefore it can reduce the waiting bus time of GE and RE and improve the efficient of bus communication.

Zugl.: Lübeck, Univ., Diss., 2009

abstract: Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction. SystemC TLM2.0 provides the capability to model hardware design at higher levels of abstraction with trade-off of simulation speed and accuracy. In this thesis, SystemC TLM2.0 models of NoC routers are developed at three levels of abstraction namely loosely-timed, approximately-timed, and cycle accurate. Simulation speed and accuracy of these three models are evaluated by a case study of a 4x4 mesh NoC. / Dissertation/Thesis / M.S. Electrical Engineering 2012