Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes 2/3rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using SystemC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs other parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers. / Master of Science

Les systèmes embarqués sont de plus en plus intégrés dans les applications temps réel actuelles. Ils sont généralement constitués de composants matériels et logiciels profondément Intégrés mais hétérogènes. Ces composants sont développés sous des contraintes très strictes. En conséquence, le travail des ingénieurs de conception est devenu plus difficile. Pour répondre aux normes de haute qualité dans les systèmes embarqués de nos jours et pour satisfaire aux besoins quotidiens de l'industrie, l'automatisation du processus de développement de ces systèmes prend de plus en plus d'ampleur. Un défi majeur est de développer une approche automatisée qui peut être utilisée pour la vérification intégrée et la validation de systèmes complexes et hétérogènes.Dans le cadre de cette thèse, nous proposons une nouvelle approche compositionnelle pour la modélisation et la vérification des systèmes complexes décrits en langage SystemC. Cette approche est basée sur le modèle des SystemC Waiting State Automata (WSA). Les SystemC Waiting State Automata sont des automates permettant de modéliser le comportement abstrait des systèmes matériels et logiciels décrits en SystemC tout en préservant la sémantique de l'ordonnanceur SystemC au niveau des cycles temporels et au niveau des delta-cycles. Ce modèle permet de réduire la complexité de la modélisation des systèmes complexes due au problème de l'explosion combinatoire tout en restant fidèle au système initial. Ce modèle est compositionnel et supporte le rafinement. De plus, il est étendu par des paramètres temps ainsi que des compteurs afin de prendre en compte les aspects relatifs à la temporalité et aux propriétés fonctionnelles comme notamment la qualité de service. Nous proposons ensuite une chaîne de construction automatique des WSAs à partir de la description SystemC. Cette construction repose sur l'exécution symbolique et l'abstraction des prédicats. Nous proposons un ensemble d'algorithmes de composition et de réduction de ces automates afin de pouvoir étudier, analyser et vérifier les comportements concurrents des systèmes décrits ainsi que les échanges de données entre les différents composants. Nous proposons enfin d'appliquer notre approche dans le cadre de la modélisation et la simulation des systèmes complexes. Ensuite l'expérimenter pour donner une estimation du pire temps d'exécution (worst-case execution time (WCET)) en utilisant le modèle du Timed SystemC WSA. Enfin, on définit l'application des techniques du model checking pour prouver la correction de l'analyse abstraite de notre approche. / Embedded systems are increasingly integrated into existing real-time applications. They are usually composed of deeply integrated but heterogeneous hardware and software components. These components are developed under strict constraints. Accordingly, the work of design engineers became more tricky and challenging. To meet the high quality standards in nowadays embedded systems and to satisfy the rising industrial demands, the automatization of the developing process of those systems is gaining more and more importance. A major challenge is to develop an automated approach that can be used for the integrated verification and validation of complex and heterogeneous HW/SW systems.In this thesis, we propose a new compositional approach to model and verify hardware and software written in SystemC language. This approach is based on the SystemC Waiting State Automata (WSA). The SystemC Waiting State Automata are used to model the abstract behavior of hardware or software systems described in SystemC. They preserve the semantics of the SystemC scheduler at the temporal and the delta-cycle level. This model allows to reduce the complexity of the modeling process of complex systems due to the problem of state explosion during modeling while remaining faithful to the original system. The SystemC waiting state automaton is also compositional and supports refinement. In addition, this model is extended with parameters such as time and counters in order to take into account further aspects like temporality and other extra-functional properties such as QoS.In this thesis, we propose a stepwise approach on how to automatically extract the SystemC WSAs from SystemC descriptions. This construction is based on symbolic execution together with predicate abstraction. We propose a set of algorithms to symbolically compose and reduce the SystemC WSAs in order to study, analyze and verify concurrent behavior of systems as well as the data exchange between various components. We then propose to use the SystemC WSA to model and simulate hardware and software systems, and to compute the worst cas execution time (WCET) using the Timed SystemC WSA. Finally, we define how to apply model checking techniques to prove the correctness of the abstract analysis.

Made available in DSpace on 2014-12-17T15:48:06Z (GMT). No. of bitstreams: 1 SergioQM.pdf: 363127 bytes, checksum: 7b8fb995a67b3e514e8b774e59124df3 (MD5) Previous issue date: 2006-03-03 / New programming language paradigms have commonly been tested and eventually incorporated into hardware description languages. Recently, aspect-oriented programming (AOP) has shown successful in improving the modularity of object-oriented and structured languages such Java, C++ and C. Thus, one can expect that, using AOP, one can improve the understanding of the hardware systems under design, as well as make its components more reusable and easier to maintain. We apply AOP in applications developed using the SystemC library. Several examples will be presented illustrating how to combine AOP and SystemC. During the presentation of these examples, the benefits of this new approach will also be discussed / Novos paradigmas de linguagens de programa??o v?em sendo comumente testados e geralmente s?o incorporados depois por linguagens de descri??o de hardware. Recentemente, a programa??o orientada a aspectos (POA) provou ser ?til na tentativa de melhorar a modularidade de linguagens estruturadas e orientadas a objeto tais como Java, C++ e C. Diante de tal fato, podemos esperar que o uso de POA pode melhorar o entendimento de sistemas hardware que est?o sendo projetados, bem como tornar seus componentes mais reus?veis e f?ceis de manter. Iremos abordar ent?o o uso de POA em aplica??es desenvolvidas utilizando a biblioteca SystemC. Ser?o apresentados v?rios exemplos que ilustram o uso de POA juntamente com SystemC, mostrando alternativas e discutindo os seus benef?cios

Les systèmes sur puce sont de plus en plus complexes : ils intègrent des parties numériques, desparties analogiques et des capteurs ou actionneurs. SystemC et son extension SystemC AMSpermettent aujourd’hui de modéliser à haut niveau d’abstraction de tels systèmes. Ces outilsconstituent de véritables atouts dans une optique d’étude de faisabilité, d’exploration architecturale etde vérification du fonctionnement global des systèmes complexes hétérogènes et multiphysiques. Eneffet, les durées de simulation deviennent trop importantes pour envisager les simulations globales àbas niveau d’abstraction. De plus, les simulations basées sur l’utilisation conjointe de différents outilsprovoquent des problèmes de synchronisation. Les modèles de bas niveau, une fois crées par lesspécialistes des différents domaines peuvent toutefois être abstraits afin de générer des modèles dehaut niveau simulables sous SystemC/SystemC AMS en des temps de simulation réduits. Une analysedes modèles de calcul et des styles de modélisation possibles est d’abord présentée afin d’établir unlien avec les durées de simulation, ceci pour proposer un style de modélisation en fonction du niveaud’abstraction souhaité et de l’ampleur de la simulation à effectuer. Dans le cas des circuits analogiqueslinéaires, une méthode permettant de générer automatiquement des modèles de haut niveaud’abstraction à partir de modèles de bas niveau a été proposée. Afin d’évaluer très tôt dans le flot deconception la consommation d’un système, un moyen d’enrichir les modèles de haut niveaupréalablement générés est présenté. L’attention a ensuite été portée sur la modélisation à haut niveaudes systèmes multiphysiques. Deux méthodes y sont discutées : la méthode consistant à utiliser lecircuit équivalent électrique puis la méthode basée sur les bond graphs. En particulier, nous proposonsune méthode permettant de générer un modèle équivalent au bond graph à partir d’un modèle de basniveau. Enfin, la modélisation d’un système éolien est étudiée afin d’illustrer les différents conceptsprésentés dans cette thèse. / Systems on chip are more and more complex as they now embed not only digital and analog parts, butalso sensors and actuators. SystemC and its extension SystemC AMS allow the high level modeling ofsuch systems. These tools are efficient for feasibility study, architectural exploration and globalverification of heterogeneous and multiphysics systems. At low level of abstraction, the simulationdurations are too important. Moreover, synchronization problems appear when cosimulations areperformed. It is possible to abstract the low level models that are developed by the specialists of thedifferent domains to create high level models that can be simulated faster using SystemC/SystemCAMS. The models of computation and the modeling styles have been studied. A relation is shownbetween the modeling style, the model size and the simulation speed. A method that generatesautomatically the high level model of an analog linear circuit from its low level representation isproposed. Then, it is shown how to include in the high level model some information allowing thepower consumption estimation. After that, the multiphysics systems modeling is studied. Twomethods are discussed: firstly, the one that uses the electrical equivalent circuit, then the one based onthe bond graph approach. It is shown how to generate a bond graph equivalent model from a low levelrepresentation. Finally, the modeling of a wind turbine system is discussed in order to illustrate thedifferent concepts presented in this thesis.

Cette thèse traite de la modélisation et la simulation de réseaux de capteurs sans fil afin de fournir des estimations précises de consommations d´énergie. Un cadre de conception et de simulation base sur SystemC au niveau système est proposé, nommé IDEA1. Elle permet l’exploration de l’espace de conception de réseaux de capteurs à un stade amont. Les résultats de simulation comprennent le taux de livraison de paquets, la latence de transmission et les consommations d’énergie. Sur un banc d’essai comportant 9 nœuds, la différence moyen entre les IDEA1 simulations et les mesures expérimentales est 4.6 %. Les performances d'IDEA1 sont comparées avec un autre simulateur largement utilisé, NS-2. Avec la co-simulation matérielle et logicielle, IDEA1 peut apporter des modèles plus détaillés de nœuds de capteurs. Pour fournir les résultats de la simulation au même niveau d’abstraction, IDEA1 réalise les simulations deux fois plus vite que NS-2.Enfin, deux études de cas sont accomplies pour valider le flot de conception d'IDEA1. La performance de l‘IEEE 802.15.4 est globalement évaluée pour diverses charges de trafic et configurations de paramètres de protocole. Une application de contrôle actif des vibrations est également étudiée. Les simulations d'IDEA1 trouvent le meilleur choix de protocoles de communication. / This thesis deals with the modeling and simulation of wireless sensor networks in order to provide mote accurate prediction of energy consumptions. A SystemC-based system level design and simulation framework is proposed, named as IDEA1. It enables the design space exploration of sensor networks at an early stage. The simulation results include packet delivery rate, transmission latency and energy consumptions. A testbed consisting of 9 motes is built to validate the simulation results of IDEA1. The average deviation between the IDEA1 simulations and the experimental measurements is 4.6%. The performances of IDEA1 are compared with a widely-used WSN simulator,NS-2. With the hardware and software co-simulation, IDEA1 can provide more detailed models of sensor nodes. For offering the simulation results at same abstraction level,IDEA1 only uses one third of the simulation time of NS-2. Finally, two case studies are performed to validate design flow of IDEA1. The performance of IEEE 802.15.4sensor networks is comprehensively evaluated for various traffic loads and configurations of protocol parameters. In addition, a real-time active vibration control application is also studied. By the simulation of IDEA1, the best choice of communication protocols and hardware platforms is found.

Les systèmes embarqués sont de plus en plus intégrés dans les applications temps réel actuelles. Ils sont généralement constitués de composants matériels et logiciels profondément Intégrés mais hétérogènes. Ces composants sont développés sous des contraintes très strictes. En conséquence, le travail des ingénieurs de conception est devenu plus difficile. Pour répondre aux normes de haute qualité dans les systèmes embarqués de nos jours et pour satisfaire aux besoins quotidiens de l'industrie, l'automatisation du processus de développement de ces systèmes prend de plus en plus d'ampleur. Un défi majeur est de développer une approche automatisée qui peut être utilisée pour la vérification intégrée et la validation de systèmes complexes et hétérogènes.Dans le cadre de cette thèse, nous proposons une nouvelle approche compositionnelle pour la modélisation et la vérification des systèmes complexes décrits en langage SystemC. Cette approche est basée sur le modèle des SystemC Waiting State Automata (WSA). Les SystemC Waiting State Automata sont des automates permettant de modéliser le comportement abstrait des systèmes matériels et logiciels décrits en SystemC tout en préservant la sémantique de l'ordonnanceur SystemC au niveau des cycles temporels et au niveau des delta-cycles. Ce modèle permet de réduire la complexité de la modélisation des systèmes complexes due au problème de l'explosion combinatoire tout en restant fidèle au système initial. Ce modèle est compositionnel et supporte le rafinement. De plus, il est étendu par des paramètres temps ainsi que des compteurs afin de prendre en compte les aspects relatifs à la temporalité et aux propriétés fonctionnelles comme notamment la qualité de service. Nous proposons ensuite une chaîne de construction automatique des WSAs à partir de la description SystemC. Cette construction repose sur l'exécution symbolique et l'abstraction des prédicats. Nous proposons un ensemble d'algorithmes de composition et de réduction de ces automates afin de pouvoir étudier, analyser et vérifier les comportements concurrents des systèmes décrits ainsi que les échanges de données entre les différents composants. Nous proposons enfin d'appliquer notre approche dans le cadre de la modélisation et la simulation des systèmes complexes. Ensuite l'expérimenter pour donner une estimation du pire temps d'exécution (worst-case execution time (WCET)) en utilisant le modèle du Timed SystemC WSA. Enfin, on définit l'application des techniques du model checking pour prouver la correction de l'analyse abstraite de notre approche. / Embedded systems are increasingly integrated into existing real-time applications. They are usually composed of deeply integrated but heterogeneous hardware and software components. These components are developed under strict constraints. Accordingly, the work of design engineers became more tricky and challenging. To meet the high quality standards in nowadays embedded systems and to satisfy the rising industrial demands, the automatization of the developing process of those systems is gaining more and more importance. A major challenge is to develop an automated approach that can be used for the integrated verification and validation of complex and heterogeneous HW/SW systems.In this thesis, we propose a new compositional approach to model and verify hardware and software written in SystemC language. This approach is based on the SystemC Waiting State Automata (WSA). The SystemC Waiting State Automata are used to model the abstract behavior of hardware or software systems described in SystemC. They preserve the semantics of the SystemC scheduler at the temporal and the delta-cycle level. This model allows to reduce the complexity of the modeling process of complex systems due to the problem of state explosion during modeling while remaining faithful to the original system. The SystemC waiting state automaton is also compositional and supports refinement. In addition, this model is extended with parameters such as time and counters in order to take into account further aspects like temporality and other extra-functional properties such as QoS.In this thesis, we propose a stepwise approach on how to automatically extract the SystemC WSAs from SystemC descriptions. This construction is based on symbolic execution together with predicate abstraction. We propose a set of algorithms to symbolically compose and reduce the SystemC WSAs in order to study, analyze and verify concurrent behavior of systems as well as the data exchange between various components. We then propose to use the SystemC WSA to model and simulate hardware and software systems, and to compute the worst cas execution time (WCET) using the Timed SystemC WSA. Finally, we define how to apply model checking techniques to prove the correctness of the abstract analysis.

<p>This thesis describes the design and implementation of a Digital Audio Broadcasting (DAB) System developed using C++ Language and SystemC libraries. The main aspects covered within this report are the data structure of DAB system, and some interesting points of SystemC Library very useful for the implementation of the final system. </p><p>It starts with a introduction of DAB system and his principals advantages. Next it goes further into the definition of data structures of DAB, they are FIC, MSC, and DAB audio frame, explained with MPEG and PAD packets. Later on this chapter there is an explanation of the SystemC library with special attention on the features that I used to implement the system. This features are the events used in the communication between processes and the interfaces needed for sending and receiving the data.</p><p>With all these points covered is quite easy for a reader to understand the implementation of the system, despite this point is covered in the last chapter of the thesis. The implementation is here explained in two different steps. The first one explain how is formed the DAB audio frame by means of MPEG frames that are wrote in channel by producer interface, this frames are readed by consumer interface. For this purpose I have created some classes and structures that are explained in this part. The second part explain how I obtain the DAB transmission frame which is obtained creating MSC frames, that are big data structures formed by groups of DAB audio frames, therefore there are some functions that act like a buffer and add audio frames to the MSC data structure. Of independent way there is the FIC frame that is generated of random way and its added to the transmission frame.</p>

This thesis describes the design and implementation of a Digital Audio Broadcasting (DAB) System developed using C++ Language and SystemC libraries. The main aspects covered within this report are the data structure of DAB system, and some interesting points of SystemC Library very useful for the implementation of the final system. It starts with a introduction of DAB system and his principals advantages. Next it goes further into the definition of data structures of DAB, they are FIC, MSC, and DAB audio frame, explained with MPEG and PAD packets. Later on this chapter there is an explanation of the SystemC library with special attention on the features that I used to implement the system. This features are the events used in the communication between processes and the interfaces needed for sending and receiving the data. With all these points covered is quite easy for a reader to understand the implementation of the system, despite this point is covered in the last chapter of the thesis. The implementation is here explained in two different steps. The first one explain how is formed the DAB audio frame by means of MPEG frames that are wrote in channel by producer interface, this frames are readed by consumer interface. For this purpose I have created some classes and structures that are explained in this part. The second part explain how I obtain the DAB transmission frame which is obtained creating MSC frames, that are big data structures formed by groups of DAB audio frames, therefore there are some functions that act like a buffer and add audio frames to the MSC data structure. Of independent way there is the FIC frame that is generated of random way and its added to the transmission frame.

Die Dissertationsschrift stellt eine Toolkette zum abstrakten Entwurf von Mikrosystemen vor. Mikrosysteme können aus Elementen verschiedener physikalischer Domänen bestehen und zusätzlich digitale Hardware sowie Software enthalten. Die Erfassung und Formalisierung dieser heterogenen Systeme stellt den ersten Schritt im Entwurfsprozess dar, die damit verbundene neue Methodik des Designs von Mikrosystemen bildet den Kern der vorliegenden Arbeit. Zur Erfassung der analogen Spezifikationsteile enthält die Arbeit die Schilderung und Implementierung neuer Datenstrukturen, die ausgehend von einer ausführlichen Anforderungsanalyse geschaffen wurden. Das abstrakte Systemverhalten wird mit Hilfe hybrider Automaten modelliert, die sowohl mit speziellen hybriden Werkzeugen als auch mit SystemC-AMS simulierbar sind. Darüber hinaus beschäftigt sich die Arbeit mit der Erfassung von Signalverläufen und Schaltplaninformationen. Die formalisierten Anforderungen ermöglichen erste Prüfungen der Spezifikation auf Konsistenz. Zur Unterstützung niedriger Abstraktionsebenen wie der Differentialgleichungsebene steht ein Wandler von SystemC-AMS nach VHDL-AMS bereit. In die Systembeschreibung mit SystemC-AMS ist die Definition und Verknüpfung von Kostenparametern integrierbar. Das daraus entstehende globale Gütemaß hilft dem Entwerferteam, die optimale Systemrealisierung zu finden. / The PhD thesis proposes a toolflow for the design of microsystems on higher abstraction levels. Microsystems may consist of components using effects in different physical domains plus additional digital hardware and software. The collection and formalization of these heterogeneous systems is a first step in the design process, the associated design method ist the key point of this work. The system behavior is modeled using hybrid automata, which are checkable using hybrid modelcheckers and simulable using SystemC-AMS. Furthermore the work deals with signal forms and circuit parameters. To support modeling on lower abstraction levels like differential algebraic equations a syntax conversion from SystemC-AMS to VHDL-AMS was included. The integration of cost factors into SystemC-AMS allows design space exploration during system simulation.

The fields of System-On-Chip (SOC) and Embedded Systems Design have received a lot of attention in the last years. As part of an effort to increase productivity and reduce the time-to-market of new products, different approaches for Electronic System-Level Design frameworks have been proposed. These different methods promise a transparent co-design of hardware and software without having to focus on the final hardware/software split. In our work, we focused on enhancing the component database, modeling and synthesis capabilities of the System-On-Chip Environment (SCE). We investigated two different virtual platform emulators (QEMU and OVP) for integration into SCE. Based on a comparative analysis, we opted on integrating the Open Virtual Platforms (OVP) models and tested the enhanced SCE simulation, design and synthesis capabilities with a JPEG encoder application, which uses both custom hardware and software as part of the system. Our approach proves not only to provide fast functional verification support for designers (10+ times faster than cycle accurate models), but also to offer a good speed/accuracy relationship when compared against integration of cycle accurate or behavioral (host-compiled) models. / text