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Electronic applications have expanded to encompass a variety of materials. In particular, allotropes of carbon interest researchers for their electronic applications. Knowledge of carbon allotropes and their applications has expanded significantly since the discovery of C60 Buckminsterfullerene in 1985, the discovery of multi- and single-walled carbon nanotubes in the early 1990s, and the isolation of graphene in 2004. Single-walled carbon nanotubes (SWNTs) have the potential to bring next-generation electronic devices to fruition. Such devices could be flexible, conformable, and inexpensive. SWNT-based electronics are promising for chemical and biological sensing applications, for example, where high carrier mobilities are unnecessary, and material conformity and inexpensive processing are significant advantages. Considerable progress has been made in separating semiconducting SWNTs from metallic SWNTs, enabling SWNT incorporation into semiconducting electronic technologies. Selective sorting of semiconducting SWNTs using π-conjugated polymers is an effective and efficient technique to enrich large quantities of ultra-pure semiconducting SWNTs. Following semiconducting enrichment, SWNTs can be incorporated into electronic devices. This thesis focuses on the enrichment of semiconducting SWNTs via conjugated polymer extraction and incorporating the resulting polymer-SWNT dispersions into thin-film transistors (TFTs). Novel copolymers were investigated for their capacity to selectively sort and disperse large-diameter sc-SWNTs synthesized using the plasma torch technique. Absorption and Raman spectroscopy were employed to monitor the efficacy of the conjugated polymer extraction procedure. Following enrichment, the polymer-SWNT dispersions were incorporated into TFTs. The interaction between the conjugated polymer and the SWNT and the conjugated polymer and dielectric was an essential component of TFT optimization. Furthermore, the procedure of sorting and dispersing sc-SWNTs is investigated for its effect on TFT performance and was another component of TFT optimization. TFTs were electrically characterized in terms of carrier mobility, threshold voltage, hysteresis, and current on/off ratio. The film morphology of the SWNT TFTs was also investigated. Atomic force microscopy and Raman mapping were used to provide insight into the nanometre and micrometre scale film morphology, respectively.

Current AlGaN/GaN Heterojunction Field Effect Transistors (HFETs) make use of multiple sources, drains, and gates in parallel to maximize transconductance and effective gain while minimizing the current density through each channel. To connect the sources to a common ground, current practice prescribes the fabrication of air bridges above the gates and drains. This practice has the advantage of a low dielectric constant and low parasitic capacitance, but it is at the expense of manufacturability and robust device operation. In the study described below, the air bridges in AlGaN/GaN HFETs were replaced by a polymer supported metallization bridge with the intention of improving ease of fabrication and reliability. The DC, high frequency, and power performance for several polymer step heights were investigated. The resultant structures were functional and robust; however, their electrical performance was degraded due to high source resistance. The cause of the high source resistance was found to be thinning of the metallization at the polymer step. The effect was more pronounced for higher step heights. / Master of Science

Le travail réalisé au cours de cette thèse porte sur l’optimisation du transistor bipolaire à hétérojonction Si/SiGe:C pour les applications d’amplification de puissance pour les communications sans fils. Nous présentons tout d’abord la structure d’étude. Il s’agit du transistor bipolaire à hétérojonction Si/SiGe:C intégré en technologie BiCMOS 0.25µm sur plaques 200mm. La cellule dédiée à l’amplification de puissance est présentée. Une attention particulière est apportée aux phénomènes thermiques inhérents à ce type de cellules ainsi qu’aux solutions mises en œuvre pour les atténuer. Les diverses optimisations réalisées sur l’architecture du TBH sont détaillées. Ces optimisations touchent à la fois à la modification du procédé technologique et au dessin du transistor. Notre étude porte sur l’amélioration des performances petit et grand signal via l’optimisation des paramètres technologiques définissant la structure épitaxiale intrinsèque de base et de collecteur ainsi que des règles de dessin du transistor. Enfin, deux types d’architectures de TBH développées sont présentées. L’une de type simple polysilicium quasi auto-alignée qui s’intègre dans une technologie dédiée à l’amplification de puissance, l’autre présentant une structure double polysilicium également auto-alignée. / The present work deals with Si/SiGe:C heterojonction bipolar transistor optimization for power amplifier applications dedicated to wireless communications. We first present the investigated structure, a Si/SiGe:C heterojonction bipolar transistor integrated in a 0.25µm BiCMOS technology on 200 mm wafers. We discuss the cell dedicated to power amplification. We have paid attention to thermal phenomenon linked to this kind of cell and to possible dedicated solutions. Various optimizations realized on HBT architecture are detailed. These optimizations concern technological process modifications and transistor design. The main objective of this work is to improve both large and small signal characteristics. This is obtained by transistor design rule variations, collector and base intrinsic parameters optimization. Finally, two kind of developed HBT architectures are presented. One, simple polysilicium quasi self aligned, integrated in a technology dedicated to power amplification, the other one fully self aligned with double polysilicium structure.

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produits. / Reliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation.