Avec l'évolution des technologies et le développement des objets connectés, la consommation des circuits est devenue un sujet important. Dans cette thèse nous nous concentrons sur la consommation des mémoires non volatiles à piégeage de charge. Afin de diminuer la consommation, différentes architectures ont vu le jour comme les mémoires 2T ou Split Gate. Nous proposons deux nouvelles architectures de mémoires permettant la diminution de la consommation par rapport à une mémoire Flash standard. La première, appelée ATW (Asymmetrical Tunnel Window), est composée d'une marche d'oxyde au niveau de son oxyde tunnel qui lui permet d'être moins consommatrice qu'une mémoire Flash standard. Une seconde architecture mémoire appelée eSTM (embedded Select Trench Memory) est aussi présentée. Son principal atout est la présence de son transistor de sélection qui est indispensable pour avoir une faible consommation. Grâce à son architecture, cette cellule est bien meilleure que l'architecture proposée précédemment (ATW). Une dernière étude a été réalisée afin d'optimiser le procédé de fabrication de la mémoire eSTM pour le rendre plus robuste. / With the evolution of technologies and the development of connected objects, the circuit consumption is becoming an important subject. In this thesis, we focus on the consumption of trap-charge non-volatile memories. To decrease the consumption, different architectures have emerged, like 2T or Split Gate memories. We propose two new memory architectures allowing to decrease the consumption compared to the standard Flash memory. The first, called ATW (Asymmetrical Tunnel Window), is composed of an oxide step in the tunnel oxide which allows to be less consumer than a standard Flash memory. A second memory architecture called eSTM (embedded Select Trench Memory) is also presented. Its main advantage is its select transistor which is essential to obtain a lower consumption. Thanks to its architecture, this cell is better than the previously proposed architecture (ATW). The last study has been performed to optimize the process flow of the eSTM memory to make it more robust.

Ce manuscrit porte sur la conception d’un transistor à effet de champ destiné à l’observation de la photoluminescence de l’exciton et des complexes excitoniques chargés du ZnO sous l’influence d’un champ électrique. Pour cela, des simulations ont permis de définir un cahier des charges de la structure du transistor afin de bloquer la conductivité dans le canal de ZnO et d’appliquer un champ électrique intense. La seconde partie concerne le choix du matériau de grille et de l’électrode transparente de surface pour l’observation de la photoluminescence dans le canal. L’oxyde de gallium (-Ga2O3) a été choisi car il présente un grand gap, des propriétés d’isolant et de semi-conducteur avec dopage. Cependant les films de Ga2O3 dopés avec Ti, Sn, Zn et Mg élaborés par MOCVD n’ont pas révélé de conductivité. Les films d’alliages (Ga,Sn)2O3 n’ont pas non plus montré de conductivité et leur structure est étudiée intensivement. Des traitements plasma radiofréquence sous flux d’argon, d’oxygène ou d’hydrogène ont permis de montrer que l’implantation de l’hydrogène donne lieu à un niveau donneur avec une énergie d’activation de 7 meV. La conductivité est toutefois modulée par le dopage en Sn et les traitements s’accompagnent d’un changement de la sous-stœchiométrie en oxygène qui diminue la transparence à cause de la formation de niveau profond de lacune d’oxygène. La structure finale de la grille transparente dans l’ultraviolet pour l’observation de la photoluminescence du ZnO peut donc être élaborée par une grille diélectrique de -Ga2O3 puis une électrode conductrice transparente de (Ga,Sn)2O3 traitée superficiellement par un plasma d’hydrogène. / This manuscript covers the design of a field transistor for the observation of photoluminescence of the exciton and the charged excitonic complex of ZnO under the influence of an electric field. For this, simulations have helped to define the specifications of the transistor structure to block the conductivity in the ZnO channel and applying a strong electric field. The second part concerns the choice of gate material and the surface transparent electrode for the observation of photoluminescence in the channel. The gallium oxide (-Ga2O3) was chosen because it has a large gap, insulating properties and semiconductor properties with doping. However, Ga2O3 films doped with Ti, Sn, Zn and Mg MOCVD did not show conductivity. Films of alloys (Ga,Sn)2O3 have not shown either conductivity and their structure is studied intensively. Radio frequency plasma treatment under a flux of argon, oxygen or hydrogen have shown that implantation of hydrogen gives rise to a donor level with 7 meV activation energy. However, the conductivity is modulated by doping Sn and treatments are accompanied by a change of sub-stoichiometry in oxygen, which reduces the transparency due to the formation of deep level of oxygen vacancy. The final structure of the transparent gate in the ultraviolet for the observation of photoluminescence of ZnO can be prepared by a dielectric gate -Ga2O3 and a transparent conductive electrode of (Ga,Sn)2O3 surface treated by a plasma of hydrogen.

O transistor de efeito de campo de porta estendida e separada (SEGFET) é um dispositivo alternativo ao tradicional transistor de efeito de campo seletivo a íons (ISFET). A grande vantagem desse dispositivo se refere ao seu fácil processamento, ou seja, se restringe somente a manipulação do eletrodo de porta, evitando processos convencionais de microeletrônica. Neste sentido, sensores iônicos e biossensores podem ser facilmente implementados combinando materiais de reconhecimento químico e/ou biológico. Por sua vez, a técnica de fabricação de filmes finos camada por camada (layer-by-layer, LbL) se mostra versátil para manipulação de diversos tipos de materiais em nível molecular. Materiais orgânicos e inorgânicos podem ser automontados em substratos sólidos por meio da simples adsorção eletrostática formando compósitos com propriedades únicas com o objetivo de serem aplicados em sensores ou biossensores. Neste trabalho, o conceito de dispositivo SEGFET foi combinado com a técnica LbL por meio da manipulação de materiais orgânicos (polieletrólitos, dendrímeros e polianilina) e inorgânicos (TiO2 e V2O5) nanoparticulados a fim de se obter novos sensores de pH e biossensores para a detecção de glicose e uréia, dois importantes analitos de interesse clínico. Numa primeira etapa, diferentes filmes LbL foram produzidos, caracterizados e testados como camada sensível (porta estendida) em dispositivos SEGFETs. Todos os sistemas estudados se mostraram promissores como sensores de pH, ou seja, com uma sensibilidade próxima do valor teórico sugerido pela equação de Nernst (59,15 mV.pH-1). Esses resultados podem ser atribuídos à natureza anfotérica do material da última camada no filme LbL. Numa segunda etapa, as enzima glicose oxidase (GOx) e urease foram convenientemente imobilizadas nos filmes LbL. Pelo fato dessas enzimas gerarem ou consumirem prótons durante a catálise da reação, os filmes LbL modificados enzimaticamente foram utilizados em biossensores de glicose e uréia, apresentando eficiente detecção. Assim, a união de dispositivos SEGFET com a técnica de automontagem se mostrou promissora para construção de sensores e biossensores eficientes e de baixo custo. / Separative extended gate field-effect transistor (SEGFET) device is an alternative to the conventional ion-sensitive field-effect transistor (ISFET). The great advantage of SEGFET refers to its easy processing, i.e., it is limited under only manipulation of the gate electrode, avoiding the conventional microelectronic processes. In this way, ion sensors and biosensors can be easily implemented combining chemical and/or biological recognition materials. In turn, the layer-by-layer (LbL) technique shows be versatile for handling various types of materials at molecular level. In this thesis, the concept of SEGFET device was combined with the LbL technique through the manipulation of organic (polyelectrolytes, dendrimers and poly (aniline)) and inorganic materials (TiO2 and V2O5 nanoparticles) in order to get new pH sensors and biosensors for the detection of glucose and urea, two important analytes of clinical interest. In a first step, different LbL films were produced, characterized and tested as the sensitive layer (extended gate) in SEGFETs devices. All studied systems were promissing as pH sensors, i.e., with a sensitivity close to the theoretical value suggested by Nernst equation (59.15 mV.pH-1). These results can be attributed to the amphoteric nature of the material in the last layer of the LbL films. In a second step, glucose oxidase (GOx) and urease enzymes were conveniently immobilized onto LbL films. Because these enzymes generate or consume protons during catalysis of the reaction, the enzymatically modified LbL films were used in biosensors for glucose and urea, with efficient detection. Thus, the union of SEGFET devices with the LbL technique is promising to building up efficient and low-cost sensors and biosensors.

De nos jours, les caméras sont de plus en plus utilisées lors de missions spatiales ou en centrale nucléaire pour des missions d'observations (civiles ou militaires) et de surveillance (vérification du déploiement de panneaux solaires, opérations extravéhiculaires, accident nucléaire, site de stockage). L'environnement spatial, les réacteurs civils nucléaires ou les lieux de stockage de déchets radioactifs sont des milieux radiatifs qui peuvent très fortement perturber les composants électroniques et les systèmes. Dans ces environnements, les rayonnements ionisants dégradent les paramètres électriques des composants électroniques. La dose totale ionisante conduit à l'apparition d'un nombre significatif de charges dans les oxydes des matériaux constituant les composants électroniques, modifiant leurs propriétés électriques. Il en résulte qu'une exposition à la dose totale ionisante peut entraîner une défaillance partielle ou totale d'un composant voire d'un système électronique embarqué.Dans le cadre de cette thèse, nous proposons une méthode de régénération pour guérir les paramètres électriques dégradés par la dose totale ionisante de composants électroniques soumis aux rayonnements ionisants. Cette méthode consiste à appliquer des cycles de recuit isothermes à un composant électronique. Dans un premier temps, cette méthode est appliquée sur des transistors MOS, et une étude est menée sur l'impact des différents paramètres clés du recuit (polarisation, température, durée de recuit, pas en dose entre chaque recuit). Dans un second temps, nous nous intéressons à des composants plus intégrés et plus récents tels que des capteurs d'images de type CMOS APS. Nous montrons expérimentalement l'impact d'un recuit sur ce type de composant et enfin, nous adaptons la méthode de régénération pour l'appliquer à ces capteurs APS afin d'augmenter leur durée de vie. / Nowadays, cameras are more and more used in space missions or nuclear plant for observation (civil or military) and monitoring missions (checking the deployment of solar panels, extravehicular operations, nuclear accident, and area storage). The space environment, nuclear reactors or radioactive waste storage areas are radiative environments that can greatly disturb electronic components and systems. In these environments, ionizing radiation degrades the electrical parameters of electronic components. The total ionizing dose induces significant charge build-up in oxides, degrading the electrical properties of the materials of electronic devices. That can result in the loss of functionality of the entire electronic system.In this thesis, we propose a regeneration method to recover the electrical parameters degraded by total ionizing dose of electronic components subjected to ionizing radiation. In this method isothermal annealing cycles are applied to electronic devices. In a first step, this method is applied on MOS transistors, and a study is conducted on the impact of various key parameters of annealing (bias, annealing temperature, annealing time, dose step between each annealing). In a second step, we focus on components more integrated and newer such as CMOS APS image sensors. We experiment what is the impact of annealing on this type of component and finally, the regeneration method is modified to be suitable on these APS sensors to increase their lifetime.

Tecnologias submicrônicas (DSM) têm inserido novos desafios ao projeto de circuitos devido a redução de geometrias, redução na tensão de alimentação, aumento da freqüência e aumento da densidade de lógica. Estas características reduzem significativamente a confiabilidade dos circuitos integrados devido a suscetibilidade a efeitos como crosstalk e acoplamento de substrato. Ainda, os efeitos da radiação são mais significantes devido as partículas com baixa energia começam a ser um problema em tecnologias DSM. Todas essas características enfatizam a necessidade de novas ferramentas de automação. Um dos objetivos desta tese é desenvolver novas ferramentas aptas a lidar com estes desafios. Esta tese é dividida em duas grandes contribuições. A primeira está relacionada com o desenvolvimento de uma nova metodologia com o objetivo de gerar circuitos otimizados em respeito ao atraso e ao consumo de potência. Um novo fluxo de projeto é apresentado na qual o circuito é otimizado no nível de transistor. Esta metodologia permite otimizar cada transistor de acordo com as capacitâncias associadas. Diferente da metodologia tradicional, o leiaute é gerado sob demanda depois do processo de otimização de transistores. Resultados mostram melhora de 11% em relação ao atraso dos circuitos e 30% de redução no consumo de potência em comparação à metodologia tradicional. A segunda contribuição está relacionada com o desenvolvimento de técnicas de geração de circuitos tolerantes a radiação. Uma técnica CWSP é usada para aplicar redundância temporal em elementos seqüenciais. Esta técnica apresenta baixa utilização de área, mas as penalidades no atraso estão totalmente relacionadas com a duração do pulso que se planeja atenuar. Além disso, uma nova metodologia de dimensionamento de transistores para falhas transientes é apresentada. A metodologia de dimensionamento é baseada em um modelo analítico. O modelo considera independente blocos de transistores PMOS e NMOS. Então, somente transistores diretamente relacionados à atenuação são dimensionados. Resultados mostram área, atraso e consumo de potência reduzido em comparação com as técnicas CWSP e TMR, permitindo o desenvolvimento de circuitos com alta freqüência. / Deep submicron (DSM) technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. The reliability of integrated circuits is significantly reduced as a consequence of the susceptibility to crosstalk and substrate coupling. In addition, radiation effects are also more significant because particles with low energy, without importance in older technologies, start to be a problem in DSM technologies. All these characteristics emphasize the need for new Electronic Design Automation (EDA) tools. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. This methodology allows the optimization of every single transistor according to the capacitances associated to it. Different from the traditional standard cell approach, the layout is generated on demand after a transistor level optimization process. Results show an average 11% delay improvement and more than 30% power saving in comparison with the traditional design flow. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving (CWSP) technique is used to apply timing redundancy into latches and flipflops. This technique presents low area overhead, but timing penalties are totally related with the glitch duration is being attenuated. Further, a new transistor sizing methodology for Single Event Transient (SET) attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks. Thus, only transistors directly related to the SET attenuation are sized. Results show smaller area, timing and power consumption overhead in comparison with TMR and CWSP techniques allowing the development of high frequency circuits, with lower area and power overhead.

La détection de faibles concentrations d’acides nucléiques est essentielle pour certaines applications comme la biologie médicale, où elle permet le diagnostic d’une multitude de pathologies par l’identification de biomarqueurs spécifiques. Par rapport aux techniques traditionnelles de détection par voie biochimique, la détection électrique par effet de champ présente l’avantage d’être une mesure directe, sans marquage, et à réponse rapide. Les transistors à nanofils semiconducteurs sont des dispositifs prometteurs qui permettent potentiellement d’atteindre des limites de détection très basses et une sensibilité élevée, grâce à leur grand rapport surface/volume et leurs propriétés électroniques uniques. Le carbure de silicium (SiC) est un matériau semiconducteur dont les qualités le rendent particulièrement adapté aux applications visées, telles que sa très grande stabilité physico-chimique et biocompatibilité.Dans cette thèse, des transistors à effet de champ à base de nanofils de Si et SiC ont été conçus dans une approche descendante pour être fabriqués par photolithographie. Un procédé de fabrication basé sur la filière silicium a été développé et optimisé afin de réaliser des dispositifs à nanofils et à nanorubans de Si de manière reproductible. Une étude détaillée a permis de démontrer la stabilité chimique supérieure des nanofils de SiC par rapport aux nanofils de Si en conditions physiologiques. Fort de ce résultat, nous avons exploré deux approches pour l’élaboration d’une couche mince de SiC autour de ces nanostructures de Si, pour leur conférer cette résistance chimique en milieu liquide. Ces dispositifs cœur-coquille Si/SiC reproductibles ont finalement été fonctionnalisés et intégrés dans un système microfluidique complet afin de réaliser des premières mesures novatrices de détection de pH et d’ADN en temps réel et en milieu liquide. / Sensing of low concentrations of nucleic acids is essential to a variety of applications such as bio-medical analysis, in which case it allows the diagnosis of pathologies by identifying specific biomarkers. Compared to traditional sensing techniques based on biochemistry, the advantage of electrical field-effect detection is that it relies on a direct, label-free, and fast-response measurement. Transistors based on semiconducting nanowires are promising devices that theoretically enable very low detection limits and a high sensitivity, thanks to their high surface-to-volume ratio and unique electronic properties. Silicon carbide (SiC) is a semiconductor material with qualities such as very high physical and chemical stability and high biocompatibility, which make it particularly suited for aforementioned applications.In this thesis, field-effect transistors based on Si and SiC nanowires were designed with a top-down approach to be fabricated using photolithography techniques. The Si-based process was developed and optimized in order to fabricate reproducible devices made of nanowires and nanoribbons. A detailed study was conducted to demonstrate the superior chemical stability of SiC nanowires over Si nanowires under physiological conditions. Based on these results, we investigated two ways of elaborating a thin SiC layer around these Si nanostructures to provide them with its chemical resistance in liquid medium. These reproducible core-shell Si/SiC devices were eventually functionalized and integrated into a microfluidic system in order to achieve novel measurements of DNA detection in real time and in liquid media.

Le développement des transistors organiques, ces dernières années, a permis une nette amélioration de leurs performances et de leur stabilité. Ceci a été possible, notamment, grâce à une meilleure compréhension des mécanismes régissant le transport de charges dans ces dispositifs. Cependant, certains phénomènes restent encore à éclaircir, en particulier au niveau de l’interface entre le semi-conducteur et le diélectrique. Le piégeage des porteurs de charges qui est une des principales causes de perturbations du transport de charges dans les transistors organiques, en est un. Cette thèse se propose donc, d’étudier ce phénomène dans des transistors à base de pentacène.Les groupements polaires, et plus particulièrement les groupements hydroxyles, présents à l’interface entre l’isolant et le semi-conducteur, sont les principaux responsables du piégeage des porteurs de charges dans les transistors organiques. Afin de limiter leur présence, une technologie basée sur l’emploi d’une couche interfaciale diélectrique passivante, pauvre en groupements hydroxyles, à base de fluorure de calcium, a été mise en place. L’influence de cette couche sur le comportement de transistors à base de pentacène a été étudiée, de même que le vieillissement de ces dispositifs sous différentes conditions de stockage (sous vide et à l’air) et sous contrainte électrique.Ainsi, il a été mis en évidence qu’une couche de fluorure de calcium d’une épaisseur trop importante (de l’ordre de 5 nm) modifie la morphologie de la couche de pentacène, ce qui se traduit par une quasi-disparition du transport de charges dans le pentacène en configuration de transistor à effet de champ. Les études de vieillissement ont montré que sous l’effet de la couche interfaciale de CaF2, même d’une très fine épaisseur (de quelques nanomètres), une quantité plus importante d’humidité est présente dans la couche de pentacène, probablement à cause de la nature hygroscopique du fluorure de calcium. / These recent years, Organic Field-Effect Transistor (OFET) development has significantly improved it performances and it stability. This was made possible, through a better understanding of the mechanisms governing charge transport in these devices. However, some phenomena remain unclear, in particular, at the interface between the semiconductor and the dielectric. Charge carrier trapping which is one of the main causes of charge transport disturbance in organic transistors, is one of them. So, this work aims to investigate such phenomena in pentacene-based transistors.Polar groups and particularly, hydroxyl groups, located at the insulator-semiconductor interface, are the main sources of charge carriers trapping in OFET. To prevent their presence, an OFET fabrication technology based on a passivating dielectric, poor of hydroxyl groups, calcium fluoride-based interfacial layer has been developed. Effect of this layer on pentacene-based transistors operation has been studied, as well as these devices aging under different storage atmosphere (in vacuum and in air) and under electrical stress.Thus, it has been highlighted that an interfacial layer of calcium fluoride with a too high thickness (around 5 nm) changes pentacene layer morphology which results in a quasi-disappearance of charge transport in pentacene in OFET configuration. Aging studies showed that under the effect of CaF2 interfacial layer, even with a very thin thickness (a few nanometers), a greater quantity of moisture is induced in pentacene layer probably due to the hygroscopic nature of calcium fluoride.

The temperature dependent electrical characteristics of silicon carbide power transistors – 4H-SiC metal semiconductor field-effect transistors (MESFETs) and 4H-SiC bipolar junction transistors (BJTs) have been investigated through simulation and experimental approaches. Junction temperatures and temperature distributions in devices under large power densities have been estimated. The DC and RF performance of 4H-SiC RF Power MESFETs have been studied through two-dimensional electro-thermal simulations using commercial software MEDICI and ISE. The simulated characteristics of the transistors were compared with the measurement results. Performance degradation of transistors under self-heating and high operating temperatures have been analyzed in terms of gate and drain characteristics, power density, high frequency current gain and power gain. 3D thermal simulations have been performed for single and multi-finger MESFETs and the simulated junction temperatures and temperature profiles were compared with the results from electro-thermal simulations. The reduction in drain current caused by self-heating was found to be more prominent for transistors with more fingers and it imposes a limitation on both the output power and the power density (in W/mm) of multi-fingered large area devices. Thermal issues for design of high power multi-fingered SiC MESFETs were also investigated. A couple of useful ways to reduce the self-heating effects were discussed. Trap-induced performance instabilities of the devices were analyzed by carrying out DC, transient, and pulse measurements at room and elevated temperatures. Electrical characteristics of 4H-SiC BJTs have been measured. A reduction in current gain at elevated temperatures was observed. Based on the collector current-voltage diagram measured at three different ambient temperatures the junction temperature was extracted using the assumption that the current gain only depends on the temperature. Temperature measurements have been carried out for SiC BJTs. Thermal images of a device under operation were recorded using an infrared camera. 3D thermal simulations were conducted using FEMLAB. Both the simulations and the measurement showed a significant temperature increase in the vicinity of the device when operated at high power densities, thus causing the decrease of the DC current gain. The junction temperatures obtained from the thermal imaging, simulation and extraction agree well.

<p>The temperature dependent electrical characteristics of silicon carbide power transistors – 4H-SiC metal semiconductor field-effect transistors (MESFETs) and 4H-SiC bipolar junction transistors (BJTs) have been investigated through simulation and experimental approaches. Junction temperatures and temperature distributions in devices under large power densities have been estimated. </p><p>The DC and RF performance of 4H-SiC RF Power MESFETs have been studied through two-dimensional electro-thermal simulations using commercial software MEDICI and ISE. The simulated characteristics of the transistors were compared with the measurement results. Performance degradation of transistors under self-heating and high operating temperatures have been analyzed in terms of gate and drain characteristics, power density, high frequency current gain and power gain. 3D thermal simulations have been performed for single and multi-finger MESFETs and the simulated junction temperatures and temperature profiles were compared with the results from electro-thermal simulations. The reduction in drain current caused by self-heating was found to be more prominent for transistors with more fingers and it imposes a limitation on both the output power and the power density (in W/mm) of multi-fingered large area devices. Thermal issues for design of high power multi-fingered SiC MESFETs were also investigated. A couple of useful ways to reduce the self-heating effects were discussed. Trap-induced performance instabilities of the devices were analyzed by carrying out DC, transient, and pulse measurements at room and elevated temperatures. </p><p>Electrical characteristics of 4H-SiC BJTs have been measured. A reduction in current gain at elevated temperatures was observed. Based on the collector current-voltage diagram measured at three different ambient temperatures the junction temperature was extracted using the assumption that the current gain only depends on the temperature. Temperature measurements have been carried out for SiC BJTs. Thermal images of a device under operation were recorded using an infrared camera. 3D thermal simulations were conducted using FEMLAB. Both the simulations and the measurement showed a significant temperature increase in the vicinity of the device when operated at high power densities, thus causing the decrease of the DC current gain. The junction temperatures obtained from the thermal imaging, simulation and extraction agree well. </p>

PRESENTATION D'UN MODELE COMPLET, A LA FOIS STATIQUE ET DYNAMIQUE, DE TRANSISTORS DE PUISSANCE. DEVELOPPEMENT, A PARTIR DU MODELE, D'UN OUTIL NUMERIQUE DE SIMULATION DU COMPORTEMENT DYNAMIQUE "PETITS SIGNAUX". SIMULATION NUMERIQUE DU COMPORTEMENT TRANSITOIRE LARGES SIGNAUX DES TRANSISTORS DE PUISSANCE (ORGANISATION D'UN PROGRAMME DE CALCUL INTEGRANT LE TRAITEMENT DE TOUS LES ELEMENTS, STATIQUE ET DYNAMIQUE, DU MODELE, MISE AU POINT DU PROGRAMME)