Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

Today, the silicon technology is well established for RF-applications (f~1-100 GHz), with emphasis on the lower frequencies (f < 5 GHz). The field of RF power devices is extensive concerning materials and devices. One of the important RF-devices is the silicon LDMOS transistor. A large extent of the research presented in the thesis concerns studies of this device, which have resulted in increased understanding of the device behavior and improved performance. The thesis starts with a brief survey of the RF-field, including the LDMOS transistor, followed by a description of the methods used in the investigations; simulations, modeling and measurements. Specific results presented in the appended papers are also briefly summarized. A new concept for LDMOS transistors, which allows for both high frequency and high voltage operation, has been developed and characterized. World-record performance in terms of output power density was obtained: over 1 W/mm at 50 V and 3.2 GHz. Further understanding and improvements of the device are achieved using simulations and modeling. For determination of model parameters a new general parameter extraction technique was developed. The method has been successfully used for a large variety of high-frequency devices, and has been frequently used in the modeling work in this thesis. Important properties of RF-power devices are the device linearity and power efficiency. Extensive studies regarding the efficiency were conducted using numerical simulations and modeling of the off-state output resistance, which is correlated to the efficiency. The results show that significant improvements can be obtained for devices on both bulk- and SOI-substrates, using thin high-resistivity substrates and very low-resistivity SOI-substrates, respectively. Finally a new approach to drastically reduce substrate crosstalk by using very low-resistivity SOI substrate is proposed. Experimentally, a reduction of 20-40 dB was demonstrated in the GHz range compared to high-resistivity SOI substrate.

This thesis presents the results of an experimental study on single-charge effects in nanoscale Josephson junctions and Cooper pair transistors (CPTs). In nanoscale Josephson junctions the charging energy EC becomes significant at sub-Kelvin temperatures and single-charge effects, such as the Coulomb blockade of Cooper pair tunneling, influence the transport properties. In order to observe charging effects in a single Josephson junction, the impedance of the electromagnetic environment surrounding the junction has to be larger than the quantum resistance (RQ=h/4e2≈6.45kΩ). In this work the high impedance environment is obtained by biasing the sample under test (single Josephson junction or CPT) with four one-dimensional Josephson junction arrays having SQUID geometry. The advantage of this configuration is the possibility of tuning in situ the effective impedance of the electromagnetic environment. By applying a magnetic field perpendicular to the SQUID loops, the Josephson energy EJ of the SQUIDs is suppressed, resulting in an increase of the measured zero bias resistance of the arrays of several orders of magnitude (104< R0 (Ω) <109). This bias method enables the measurement of the same sample in environments with different impedance. As the impedance of the environment is increased, the current-voltage characteristics (IVCs) of the single Josephson junction and of the CPT show a well defined Coulomb blockade feature with a region of negative differential resistance, signature of the coherent tunneling of single Cooper pairs. The measured IVCs of a single Josephson junction with SQUID geometry in the high impedance environment show a qualitative agreement with the Bloch band theory as the EJ/EC ratio of the junction is tuned with the magnetic field. We also studied a single nontunable Josephson junction with strong coupling (EJ/EC > 1), where the exact dual of the overdamped Josephson effect is realized, resulting in a dual shape of the IVC, where the roles of current and voltage are exchanged. Here, we make for the first time a detailed quantitative comparison with a theory which includes the effect of fluctuations due to the finite temperature of the environment. The measurements on CPTs in the high impedance environment showed that the Coulomb blockade voltage is modulated periodically by the gate-induced charge. The gate-voltage dependence of the CPT changes from e-periodic to 2e-periodic as the impedance of the environment is increased. The high impedance environment reduces quasiparticle tunneling rates, thereby restoring the even parity of the CPT island. This behavior suggests that high impedance leads can be used to effectively suppress quasiparticle poisoning. / QC 20100928

Symmetric and fast (∼5 ms) on-to-off and off-to-on drain current switching characteristics have been obtained in screen printed organic electrochemical transistors (OECTs) including PEDOT:PSS (poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonic acid)) as the active transistor channel material. Improvement of the drain current switching characteristics is made possible by including a carbon conductor layer on top of PEDOT:PSS at the drain electrode that is in direct contact with both the channel and the electrolyte of the OECT. This carbon conductor layer suppresses the effects from a reduction front that is generated in these PEDOT:PSS-based OECTs. In the off-state of these devices this reduction front slowly migrate laterally into the PEDOT:PSS drain electrode, which make off-to-on switching slow. The OECT including carbon electrodes was manufactured using only standard printing process steps and may pave the way for fully integrated organic electronic systems that operate at low voltages for applications such as logic circuits, sensors and active matrix addressed displays. / <p>Funding Agencies|Lintec Corporation||</p>

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

In this thesis, the development of a novel experimental technique for measuring the spontaneous, stochastic work function (WF) fluctuations of conducting polymer films, at equilibrium, is discussed. Polyaniline (PANI) is studied as a representative conducting polymer. This technique utilizes an insulated-gate field-effect transistor (IGFET) with PANI gate electrode (PANI-IGFET). The fluctuations of PANI WF are transduced into measurable drain current fluctuations of the device. By analyzing these fluctuations while systematically controlling the temperature, electric field and doping level, a model of WF fluctuations in PANI films is developed. These experiments suggest that the source of WF fluctuations is the hopping of charge carriers, or trapping/detrapping of charge carriers, around the Fermi level of the PANI film at the PANI-insulator interface. This process is thermally activated with a field and doping dependent activation energy in the range of 0.1 to 0.5 eV. Thus, this new technique provides detailed information about charge-carrier dynamics in the space-charge region of the PANI film, at equilibrium. These results have important implications for organic electronics and furthering fundamental understanding of the relationship between doping, disorder and work function in organic semiconductors.

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). <br /><br /> A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 &mu;m, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. <br /><br /> An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion.

Proteins are commonly found molecules in biological systems: our fingernails, hair, skin, blood, muscle, and eyes are all made of protein. Many diseases simply arise because a protein is not folded properly. Therefore, knowledge of protein structure is considered a prerequisite to understanding protein function and, by extension, a cornerstone for drug design and for the development of therapeutic agents. Protein crystallography is a tool that allows structural biologists to discern protein structures to the highest degree of detail possible in three dimensions. The recording of x-ray diffraction data from the protein crystal is a central part of protein crystallography. As such, an important challenge in protein crystallography research is to design x-ray detectors to accurately determine the structures of proteins. This research presents the design and evaluation of a solid-state large area at panel detector for protein crystallography based on an amorphous selenium (a-Se) x-ray sensitive photoconductor operating in avalanche mode integrated with an amorphous silicon (a-Si:H) charge storage and readout pixel. The advantages of the proposed detector over the existing imaging plate (IP) and charge coupled device (CCD) detectors are large area, high dynamic range coupled to single x-ray detection capability, fast readout, high spatial resolution, and inexpensive manufacturing process. The requirement of high dynamic range is crucial for protein crystallography since both weak and strong diffraction spots need to be imaged. The main disadvantage of a-Si:H thin film transistor (TFT) array is its high electronic noise which prohibits quantum noise limited operation for the weak diffraction spots. To overcome the problem, the x-ray to charge conversion gain of a-Se is increased by using its internal avalanche multiplication gain. Since the detector can be made approximately the same size as the diffraction pattern, it eliminates the need for image demagnification. The readout time of the detector is usually within the ms range, so it is appropriate for crystallographic application. The optimal detector parameters (such as, detector size, pixel size, thickness of a-Se layer), and operating parameters (such as, electric field across the a-Se layer) are determined based on the requirements for protein crystallography. A complete model of detective quantum efficiency (DQE) of the detector is developed to predict and optimize the performance of the detector. The performance of the detector is evaluated in terms of readout time (< 1 s), dynamic range (~10^5), and sensitivity (~ 1 x-ray photon), thus validating the detector's efficacy for protein crystallography. The design of an in-house a-Si:H TFT pixel array for integration with an avalanche a-Se layer is detailed. Results obtained using single pixel are promising and highlight the feasibility of a-Si:H pixels coupled with avalanche a-Se layer for protein crystallography application.

Polymers are very attractive materials that can be tailored for specific needs and functionalities. Based on their chemical structure, they can for instance be made electrically insulating or semiconducting with specific mechanical properties. Polymers are often processable from a solution, which enables the use of conventional low-cost and high-volume manufacturing techniques to print electronic devices onto flexible substrates. A multitude of polymer-based electronic and electrochemical devices and sensors have been developed, of which some already has reached the consumer market. This thesis focuses on polarization characteristics in polyelectrolyte-based capacitor structures and their role in sensors, transistors and supercapacitors. The fate of the ions in these capacitor structures, within the polyelectrolyte and at the interfaces between the polyelectrolyte and various electronic conductors (a metal, a semiconducting polymer or a network of carbon nanotubes), is of outermost importance for the device function. The humidity-dependent polarization characteristics in a polyelectrolyte capacitor are used as the sensing probe for wireless readout of a passively operated humidity sensor circuit. This sensor circuit can be integrated into a printable low-cost passive sensor label. By varying the humidity level, limitations and possibilities are identified for polyelectrolyte-gated organic field-effect transistors. Further, the effect of the ionic conductivity is investigated for polyelectrolyte-based supercapacitors. Finally, by using an ordinary electrolyte instead of a polyelectrolyte and a high-surface area (supercapacitor) gate electrode, the device mechanisms proposed for electrolyte-gated organic transistors are unified.