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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
11

Using ordered partial decision diagrams for manufacture test generation

Cobb, Bradley Douglas 30 September 2004 (has links)
Because of limited tester time and memory, a primary goal of digital circuit manufacture test generation is to create compact test sets. Test generation programs that use Ordered Binary Decision Diagrams (OBDDs) as their primary functional representation excel at this task. Unfortunately, the use of OBDDs limits the application of these test generation programs to small circuits. This is because the size of the OBDD used to represent a function can be exponential in the number of the function's switching variables. Working with these functions can cause OBDD-based programs to exceed acceptable time and memory limits. This research proposes using Ordered Partial Decision Diagrams (OPDDs) instead as the primary functional representation for test generation systems. By limiting the number of vertices allowed in a single OPDD, complex functions can be partially represented in order to save time and memory. An OPDD-based test generation system is developed and techniques which improve its performance are evaluated on a small benchmark circuit. The new system is then demonstrated on larger and more complex circuits than its OBDD-based counterpart allows.
12

Improving systematic constraint-driven analysis using incremental and parallel techniques

Siddiqui, Junaid Haroon 25 February 2013 (has links)
This dissertation introduces Pikse, a novel methodology for more effective and efficient checking of code conformance to specifications using parallel and incremental techniques, describes a prototype implementation that embodies the methodology, and presents experiments that demonstrate its efficacy. Pikse has at its foundation a well-studied approach -- systematic constraint-driven analysis -- that has two common forms: (1) constraint-based testing -- where logical constraints that define desired inputs and expected program behavior are used for test input generation and correctness checking, say to perform black-box testing; and (2) symbolic execution -- where a systematic exploration of (bounded) program paths using symbolic input values is used to check properties of program behavior, say to perform white-box testing. Our insight at the heart of Pikse is that for certain path-based analyses, (1) the state of a run of the analysis can be encoded compactly, which provides a basis for parallel techniques that have low communication overhead; and (2) iterations performed by the analysis have commonalities, which provides the basis for incremental techniques that re-use results of computations common to successive iterations. We embody our insight into a suite of parallel and incremental techniques that enable more effective and efficient constraint-driven analysis. Moreover, our techniques work in tandem, for example, for combined black-box constraint-based input generation with white-box symbolic execution. We present a series of experiments to evaluate our techniques. Experimental results show Pikse enables significant speedups over previous state-of-the-art. / text
13

Evaluation of Automated Test Generation for Simulink : A Case Study in the Context of Propulsion Control Software

Roslund, Anton January 2020 (has links)
Automated Test Generation (ATG) has been successfully applied in many domains. For the modeling and simulation language Simulink, there has been research on developing tools for ATG with promising results. However, most tools developed as part of academic research and are not publicly available, or severely limited in their ability to be integrated into an industrial workflow. There are commercial ATG tools for Simulink, with Simulink Design Verifier (SLDV) as the de-facto standard tool. For this thesis, we perform an empirical comparison of manual tests to those generated by SLDV. For the comparison, we used 180 components from the propulsion control software developed by our industry partner. All except two components are compatible for test generation to some extent. The majority of components are partially compatible, requiring block replacement or stubbing. Approximation of floating-point numbers is the primary reason for block replacement, which can be performed automatically by SLDV. Two components were incompatible, and 14 required full stubbing of blocks. Using a pre-processing step, the generated tests achieve similar coverage as the manual tests. We performed a Mann–Whitney U test with the hypothesis that the generated tests achieve higher coverage than the manual tests. There are no statistically significant differences for either decision coverage (0.0719), or condition coverage (0.8357). However, for Modified Condition/Decision Coverage, the generated tests achieve higher coverage, and the difference is significant (0.0027). The limitations of ATG were explored by looking at the cases where the generated tests achieved lower coverage than the manual test. We found that the use of floating-point arithmetic and temporal logic increases the time required for test generation, and causes the analysis to hit the time limit. The test generation does not support all custom S-functions and perform stubbing of these blocks. This made the tool unable to reason about persistent storage. Configuration constants have limited support, which was the reason for the coverage difference in three cases. We have concluded that while much effort is required for custom tooling and initial setup, ATG can prove useful for early fault detection in an industrial workflow. ATG would prove especially useful in an automated continuous integration workflow for integration-level conformance testing.
14

Passive interoperability testing for communication protocols

Chen, Nanxing 24 June 2013 (has links) (PDF)
In the field of networking, testing of communication protocols is an important activity to validate protocol applications before commercialisation. Generally, the services that must be provided by a protocol are described in its specification(s). A specification is generally a standard defined by standards bodies such as ISO (International Standards Organization), IETF (Internet Engineering Task Force), ITU (International Telecommunication Union), etc. The purpose of testing is to verify that the protocol implementations work correctly and guarantee the quality of the services in order to meet customers expectations. To achieve this goal, a variety of testing methods have been developed. Among them, interoperability testing is to verify that several network components cooperate correctly and provide expected services. Conformance testing verifies that a product conforms to its specification. Robustness testing determines the degree to which a system operates correctly in the presence of exceptional inputs or stressful environmental conditions. In this thesis, we focus on interoperability testing. The general architecture of interoperability testing involves a system under test (SUT), which consists of at least two implementations under test (IUT). The objectives of interoperability testing are to ensure that interconnected protocol implementations are able to interact correctly and, during their interaction, provide the services predefined in their specifications. In general, the methods of interoperability testing can be classified into two approaches: active and passive testing. Among them, active test is the most conventionally used technique, which aims to test the implementations (IUT) by injecting a series of test messages (stimuli) and observing the corresponding outputs. However, the intrusive nature of active testing is that the tester has the ability to control IUTS. This implies that the tester interrupts inevitably the normal operations of the system under test. In this sense, active testing is not a suitable technique for interoperability testing, which is often carried out in operational networks. In such context, it is difficult to insert arbitrary testing messages without affecting the normal behavior and the services of the system. On the contrary, passive testing is a technique based only on observation. The tester does not need to interact with the SUT. This allows the test to be carried out without disturbing the normal operations of the system under test. Besides, passive testing also has other advantages such as: for embedded systems to which the tester does not have direct access, test can still be performed by collecting the execution traces of the system and then detect errors by comparing the trace with the behavior of the system described in its specification. In addition, passive testing makes it possible to moniter a system over a long period, and report abnomality at any time.
15

Testų sudarymo metodų vėlinimo gedimams tyrimas / Research and Development of Test Generation Methods for Delay Faults

Radavičius, Marius 10 July 2008 (has links)
Šio darbo tikslas yra realizuoti ir ištirti funkcinių vėlinimo testų generavimo algoritmus. Gaminant programuojamuosius įrenginius visada atsiranda galimybė jog gali atsirasti vėlinimo klaidų ( įėjimo signalas dėl kažkokių priežasčių išeina vėliau nei yra numatyta ). Šiuo metu lustai naudojami civilinėje bei karinėje pramonėje įvairiems gamybos procesams valdyti, pvz: medicinoje. Vėlinimo gedimų testavimai yra labai reikšmingi tiek sistemų saugumo užtikrinime, tiek sistemos patikimumo atžvilgiu. Šiais laikais tokie reikalavimai yra keliami vis didesni, nes žmogaus saugumas yra visų svarbiausia. Realizuojamas funkcinis vėlinimo testo sudarymo algoritmas pagal pokyčius išėjimuose, kuris remiasi tik programinio prototipo pirminių įėjimų ir pirminių išėjimų reikšmėmis. Sukūrus sistemą, buvo atliktas eksperimentinis jos tyrimas. Gauti panaudoto algoritmo rezultatai yra patenkinami, kurie yra pateikti šio dokumento priede. Eksperimento metu atliekami testinių rinkinių generavimai 24 loginėms schemoms. Darbe yra 42 panaudoti paveikslėliai, 27 lentel��s bei santrumpų žodynas. Medžiaga surinkta iš penkiolikos literatūros šaltinių. / The object of this work is to research functional test generation methods for delay faults. Manufacturing of programmable chips always has possibility that in those systems will be delay faults that means: input signal for some reasons appear in the output after longer time than the time was definite. In our days, programmable chips are used in the industry for the management of various civil and military manufacturing processes, for instance medicine. Delay fault testing is very important part for the system safety and trustiness. Today those requests become higher and higher, because human safety is common importance. Created test generation algorithm of the functional test that is based solely on the primary input values and the primary output values of the programming prototype. System was tested by simple step by step model,(which is presented in the fourth part of this document). The obtained results are useful and acceptable. All results are presented in the appendix of this document. The experiment contains 24 logic schemas processed test generation algorithm. The work includes of 42 pictures, 27 tables and conceptual dictionary. 15 bibliographical sources have been used.
16

DASE: Document-Assisted Symbolic Execution for Improving Automated Test Generation

Zhang, Lei 17 June 2015 (has links)
Software testing is crucial for uncovering software defects and ensuring software reliability. Symbolic execution has been utilized for automatic test generation to improve testing effectiveness. However, existing test generation techniques based on symbolic execution fail to take full advantage of programs’ rich amount of documentation specifying their input constraints, which can further enhance the effectiveness of test generation. In this paper we present a general approach, Document-Assisted Symbolic Execution (DASE), to improve automated test generation and bug detection. DASE leverages natural language processing techniques and heuristics to analyze programs’ readily available documentation and extract input constraints. The input constraints are then used as pruning criteria; inputs far from being valid are trimmed off. In this way, DASE guides symbolic execution to focus on those inputs that are semantically more important. We evaluated DASE on 88 programs from 5 mature real-world software suites: GNU Coreutils, GNU findutils, GNU grep, GNU Binutils, and elftoolchain. Compared to symbolic execution without input constraints, DASE increases line coverage, branch coverage, and call coverage by 5.27–22.10%, 5.83–21.25% and 2.81–21.43% respectively. In addition, DASE detected 13 previously unknown bugs, 6 of which have already been confirmed by the developers.
17

Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems

Jervan, Gert January 2005 (has links)
The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.
18

Combining Discrete and Continuous Domains for SysML-Based Simulation and Test Generation / Unification des ensembles discrets et continus pour la simulation et la génération de tests à partir de modèles sysML

Gauthier, Jean-Marie 19 November 2015 (has links)
Les travaux de recherche menés au cours de cette thèse s'inscrivent dans le cadre de la modélisation, de la vérification et de la validation de systèmes complexes, critiques et multi-physiques. Ces travaux visent à combler l'écart d'abstraction entre les modèles haut-niveau, point de départ des processus MBSE (Model-Based Systems Engineering), et la simulation temps réel, clef de voûte des approches In-the-Loop. Dans ce contexte, nous proposons d'unifier, au sein d'un même modèle SysML, les aspects continus d'un système, permettant de générer de manière automatique un modèle Modelica de plus bas niveau directement exécutable (simulation), et les aspects discrets, permettant l'animation et la génération de tests par des solveurs de contraintes. Les travaux réalisés au cours de cette thèse ont permis l'étude et la réalisation d'une chaîne outillée originale permettant de simuler et de tester ce type de systèmes à partir de modèles SysML en contexte In-the-Loop. Cette démarche a été validée par deux cas d'étude concrets issus de la recherche. Le premier, issu du projet ANR Smart Blocks, nous a permis de mettre à l'épreuve la méthodologie de modélisation SysML dans le but d'effectuer des simulations de convoyeur sans contact (jets d'air). Le second cas d'étude, issu du projet Région GEOSEFA, nous a permis de valider l'approche complète (simulation et test) en contexte In-the-Loop. Celui-ci porte sur la conception et la validation d'un nouveau système énergétique hybride embarqué dans un hélicoptère. / The research conducted during this thesis fall within the scope of modeling, verification and validation of critical and complex systems. This work aims to bridge the gap between the abstract high-level models, starting point of the MBSE process (Model-Based Systems Engineering), and real-time simulation keystone of In-the-Loop processes. In this context, we propose to unify, within a SysML model, continuous aspects of a system, to automatically generate an executable Modelica model (simulation), and discrete aspects allowing animation and test generation by constraint solvers. The work done during this thesis allowed the study and the realization of an original tooled approach to simulate and test such systems from SysML models within a In-the-Loop context. This approach has been validated by two concrete case studies from research partners. The first, from the ANR Smart Blocks project, allowed us to assess the relevance of the proposed SysML modeling methodology in order to perform contact less conveyor simulations. The second case study, from the GEOSEFA Regional project has allowed us to validate the overall approach (simulation and testing) in a In-the-Loop context. It covers the design and the validation of a new energy hybrid system embedded in a helicopter.
19

Automatic Test Generation and Mutation Analysis using UPPAAL SMC

Larsson, Jonatan January 2017 (has links)
Software testing is an important process for ensuring the quality of the software. As the complexity of the software increases, traditional means of manual testing becomes increasingly more complex and time consuming. In most embedded systems, designing software with as few errors as possible is often critical. Resource usage is also of concern for proper behavior because of the very nature of embedded systems.  To design reliable and energy-efficient systems, methods are needed to detect hot points of consumption and correct them prior to deployment. To reduce testing effort, Model-based testing can be used which is one testing method that allows for automatic testing of model based systems. Model-based testing has not been investigated extensively for revealing resource usage anomalies in embedded systems. UPPAAL SMC is a statistical model checking tool which can be used to model the system’s resource usage. Currently UPPAAL SMC lacks the support for performing automatic test generation and test selection. In this thesis we provide this support with a framework for automatic test generation and test selection using mutation analysis, a method for minimizing the generated test suite while maximizing the fault coverage and a tool implementing the framework on top of the UPPAAL SMC tool. The thesis also evaluates the framework on a Brake by Wire industrial system. Our results show that we could for a Brake-by-wire system, simulated on a consumer processor with five mutants, in best case find a test case that achieved 100% mutation score within one minute and confidently identify at least one test case that achieved full mutation score within five minutes. The evaluation shows that this framework is applicable and relatively efficient on an industrial system for reducing continues resource usage target testing effort.
20

Automatic Test Generation and Mutation Analysis using UPPAAL SMC

Larsson, Jonatan January 2017 (has links)
Software testing is an important process for ensuring the quality of the software. As the complexity of the software increases, traditional means of manual testing becomes increasingly more complex and time consuming. In most embedded systems, designing software with as few errors as possible is often critical. Resource usage is also of concern for proper behavior because of the very nature of embedded systems.  To design reliable and energy-efficient systems, methods are needed to detect hot points of consumption and correct them prior to deployment. To reduce testing effort, Model-based testing can be used which is one testing method that allows for automatic testing of model based systems. Model-based testing has not been investigated extensively for revealing resource usage anomalies in embedded systems. UPPAAL SMC is a statistical model checking tool which can be used to model the system’s resource usage. Currently UPPAAL SMC lacks the support for performing automatic test generation and test selection. In this thesis we provide this support with a framework for automatic test generation and test selection using mutation analysis, a method for minimizing the generated test suite while maximizing the fault coverage and a tool implementing the framework on top of the UPPAAL SMC tool. The thesis also evaluates the framework on a Brake by Wire industrial system. Our results show that we could for a Brake-by-wire system, simulated on a consumer processor with five mutants, in best case find a test case that achieved 100% mutation score within one minute and confidently identify at least one test case that achieved full mutation score within five minutes. The evaluation shows that this framework is applicable and relatively efficient on an industrial system for reducing continues resource usage target testing effort.

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