<p>Software is finding its way into an increasing range of devices (phones, medical equipment, cars...). A challenge is to design <i>verification</i> methods to ensure correctness of software. </p><p>We focus on <i>model checking</i>, an approach in which an abstract model of the implementation and a specification of requirements are provided. The task is to answer automatically whether the system conforms with its specification.We concentrate on (i) timed systems, and (ii) parameterized systems.</p><p><i>Timed systems </i>can be modeled and verified using the classical model of timed automata. Correctness is translated to language inclusion between two timed automata representing the implementation and the specification. We consider variants of timed automata, and show that the problem is at best highly complex, at worst undecidable.</p><p>A <i>parameterized system</i> contains a variable number of components. The problem is to verify correctness regardless of the number of components. <i>Regular model checking</i> is a prominent method which uses finite-state automata. We present a semi-symbolic minimization algorithm combining the partition refinement algorithm by Paige and Tarjan with decision diagrams.</p><p>Finally, we consider systems which are both timed and parameterized: <i>Timed Petri Nets</i> (<i>TPNs</i>), and <i>Timed Networks</i> (<i>TNs</i>). We present a method for checking safety properties of TPNs based on forward reachability analysis with acceleration. We show that verifying safety properties of TNs is undecidable when each process has at least two clocks, and explore decidable variations of this problem.</p>

Efficient model checking is important in order to make this type of software verification useful for systems that are complex in their structure. If a system is too large or complex then model checking does not simply scale, i.e., it could take too much time to verify the system. This is one strong argument for focusing on making model checking faster. Another interesting aim is to make model checking so fast that it can be used for predicting scheduling decisions for real-time schedulers at runtime. This of course requires the model checking to complete within a order of milliseconds or even microseconds. The aim is set very high but the results of this thesis will at least give a hint on whether this seems possible or not. The magic card for (maybe) making this possible is called Graphics Processing Unit (GPU). This thesis will investigate if and how a model checking algorithm can be ported and executed on a GPU. Modern GPU architectures offers a high degree of processing power since they are equipped with up to 1000 (NVIDIA GTX 590) or 3000 (NVIDIA Tesla K10) processor cores. The drawback is that they offer poor thread-communication possibilities and memory caches compared to CPU. This makes it very difficult to port CPU programs to GPUs.The example model (system) used in this thesis represents a real-time task scheduler that can schedule up to three periodic self-suspending tasks. The aim is to verify, i.e., find a feasible schedule for these tasks, and do it as fast as possible with the help of the GPU.

Software is finding its way into an increasing range of devices (phones, medical equipment, cars...). A challenge is to design verification methods to ensure correctness of software. We focus on model checking, an approach in which an abstract model of the implementation and a specification of requirements are provided. The task is to answer automatically whether the system conforms with its specification.We concentrate on (i) timed systems, and (ii) parameterized systems. Timed systems can be modeled and verified using the classical model of timed automata. Correctness is translated to language inclusion between two timed automata representing the implementation and the specification. We consider variants of timed automata, and show that the problem is at best highly complex, at worst undecidable. A parameterized system contains a variable number of components. The problem is to verify correctness regardless of the number of components. Regular model checking is a prominent method which uses finite-state automata. We present a semi-symbolic minimization algorithm combining the partition refinement algorithm by Paige and Tarjan with decision diagrams. Finally, we consider systems which are both timed and parameterized: Timed Petri Nets (TPNs), and Timed Networks (TNs). We present a method for checking safety properties of TPNs based on forward reachability analysis with acceleration. We show that verifying safety properties of TNs is undecidable when each process has at least two clocks, and explore decidable variations of this problem.

Testing is the dominant verification technique used in the software industry today. The use of automatic test case execution increases, but the creation of test cases remains manual and thus error prone and expensive. To automate generation and selection of test cases, model-based testing techniques have been suggested. In this thesis two central problems in model-based testing are addressed: the problem of how to formally specify coverage criteria, and the problem of how to generate a test suite from a formal timed system model, such that the test suite satisfies a given coverage criterion. We use model checking techniques to explore the state-space of a model until a set of traces is found that together satisfy the coverage criterion. A key observation is that a coverage criterion can be viewed as consisting of a set of items, which we call coverage items. Each coverage item can be treated as a separate reachability problem. Based on our view of coverage items we define a language, in the form of parameterized observer automata, to formally describe coverage criteria. We show that the language is expressive enough to describe a variety of common coverage criteria described in the literature. Two algorithms for test case generation with observer automata are presented. The first algorithm returns a trace that satisfies all coverage items with a minimum cost. We use this algorithm to generate a test suite with minimal execution time. The second algorithm explores only states that may increase the already found set of coverage items. This algorithm works well together with observer automata. The developed techniques have been implemented in the tool CoVer. The tool has been used in a case study together with Ericsson where a WAP gateway has been tested. The case study shows that the techniques have industrial strength.

Les systèmes dynamiques présentent des comportements temporels qui peuvent être exprimés sous diverses formes séquentielles telles que des signaux, des ondes, des séries chronologiques et des suites d'événements. Détecter des motifs sur de tels comportements temporels est une tâche fondamentale pour comprendre et évaluer ces systèmes. Étant donné que de nombreux comportements du système impliquent certaines caractéristiques temporelles, le besoin de spécifier et de détecter des motifs de comportements qui implique des exigences de synchronisation, appelées motifs temporisés, est évidente.Cependant, il s'agit d'une tâche non triviale due à un certain nombre de raisons, notamment la concomitance des sous-systèmes et la densité de temps.La contribution principale de cette thèse est l'introduction et le développement du filtrage par motif temporisé, c'est-à-dire l'identification des segments d'un comportement donné qui satisfont un motif temporisé. Nous proposons des expressions rationnelles temporisées (TRE) et la logique de la boussole métrique (MCL) comme langages de spécification pour motifs temporisés. Nous développons d'abord un nouveau cadre qui abstraite le calcul des aspects liés au temps appelé l'algèbre des relations temporisées. Ensuite, nous fournissons des algorithmes du filtrage hors ligne pour TRE et MCL sur des comportements à temps dense à valeurs discrètes en utilisant ce cadre et étudions quelques extensions pratiques.Il est nécessaire pour certains domaines d'application tels que le contrôle réactif que le filtrage par motif doit être effectué pendant l'exécution réelle du système. Pour cela, nous fournissons un algorithme du filtrage en ligne pour TREs basé sur la technique classique des dérivées d'expressions rationnelles. Nous croyons que la technique sous-jacente qui combine les dérivées et les relations temporisées constitue une autre contribution conceptuelle majeure pour la recherche sur les systèmes temporisés.Nous présentons un logiciel libre Montre qui implémente nos idées et algorithmes. Nous explorons diverses applications du filtrage par motif temporisé par l'intermédiaire de plusieurs études de cas. Enfin, nous discutons des orientations futures et plusieurs questions ouvertes qui ont émergé à la suite de cette thèse. / Dynamical systems exhibit temporal behaviors that can be expressed in various sequential forms such as signals, waveforms, time series, and event sequences. Detecting patterns over such temporal behaviors is a fundamental task for understanding and assessing these systems. Since many system behaviors involve certain timing characteristics, the need to specify and detect patterns of behaviors that involves timing requirements, called timed patterns, is evident. However, this is a non-trivial task due to a number of reasons including the concurrency of subsystems and density of time.The key contribution of this thesis is in introducing and developing emph{timed pattern matching}, that is, the act of identifying segments of a given behavior that satisfy a timed pattern. We propose timed regular expressions (TREs) and metric compass logic (MCL) as timed pattern specification languages. We first develop a novel framework that abstracts the computation of time-related aspects called the algebra of timed relations. Then we provide offline matching algorithms for TRE and MCL over discrete-valued dense-time behaviors using this framework and study some practical extensions.It is necessary for some application areas such as reactive control that pattern matching needs to be performed during the actual execution of the system. For that, we provide an online matching algorithm for TREs based on the classical technique of derivatives of regular expressions. We believe the underlying technique that combines derivatives and timed relations constitutes another major conceptual contribution for timed systems research.Furthermore, we present an open-source tool Montre that implements our ideas and algorithms. We explore diverse applications of timed pattern matching over several case studies using Montre. Finally we discuss future directions and several open questions emerged as a result of this thesis.

Problems in formal verification are often stated in terms of finite automata and extensions thereof. In this thesis we investigate several such algorithmic problems. In the first part of the thesis we develop a theory of completeness thresholds in Bounded Model Checking. A completeness threshold for a given model M and a specification &phi; is a bound k such that, if no counterexample to &phi; of length k or less can be found in M, then M in fact satisfies &phi;. We settle a problem of Kroening et al. [KOS⁺11] in the affirmative, by showing that the linearity problem for both regular and &omega;-regular specifications (provided as finite automata and Buchi automata respectively) is PSPACE-complete. Moreover, we establish the following dichotomies: for regular specifications, completeness thresholds are either linear or exponential, whereas for &omega;-regular specifications, completeness thresholds are either linear or at least quadratic in the recurrence diameter of the model under consideration. Given a formula in a temporal logic such as LTL or MTL, a fundamental problem underpinning automata-based model checking is the complexity of evaluating the formula on a given finite word. For LTL, the complexity of this task was recently shown to be in NC [KF09]. In the second part of the thesis we present an NC algorithm for MTL, a quantitative (or metric) extension of LTL, and give an AC¹ algorithm for UTL, the unary fragment of LTL. We then establish a connection between LTL path checking and planar circuits which, among others, implies that the complexity of LTL path checking depends on the Boolean connectives allowed: adding Boolean exclusive or yields a temporal logic with P-complete path-checking problem. In the third part of the thesis we study the decidability of the reachability problem for parametric timed automata. The problem was introduced over 20 years ago by Alur, Henzinger, and Vardi [AHV93]. It is known that for three or more parametric clocks the problem is undecidable. We translate the problem to reachability questions in certain extensions of parametric one-counter machines. By further reducing to satisfiability in Presburger arithmetic with divisibility, we obtain decidability results for several classes of parametric one-counter machines. As a corollary, we show that, in the case of a single parametric clock (with arbitrarily many nonparametric clocks) the reachability problem is NEXP-complete, improving the nonelementary decision procedure of Alur et al. The case of two parametric clocks is open. Here, we show that the reachability is decidable in this case of automata with a single parameter.

La complexité croissante des systèmes embarqués nécessite des formalismes de modélisation qui peuvent être simulés et analysés pour explorer l'espace des alternatives de conception. Cette thèse décrit le développement d'un formalisme de modélisation et des outils pour l'exploration de l'espace de design au plus tôt dans le flot de conception. Nous étendons le model-checking classique au pire cas pour les automates temporisés à l'analyse stochastique basée sur un raffinement des intervalles d'incertitude temporelle par des distributions sur les délais. D'une part, nous introduisons le formalisme des Duration Probabilistic Automata (DPA) à partir duquel nous pouvons réaliser de l'analyse ainsi que de l'optimisation. D'autre part nous présentons DESPEX (Design Space Explorer), un outil d'évaluation de performance de modèles de haut niveau des applications qui s'exécutent sur les plates-formes multi-coeurs. Nous montrons également son utilisation sur plusieurs cas d'étude. / The growing complexity of embedded systems calls for modeling formalisms that can be simulated and analyzed to explore the space of design alternatives. This thesis describes the development of a modeling formalism and tools for design space exploration at early design stage.We extend the classical worst-case model checking for timed automata to stochastic analysis based on a refinement of temporal uncertainty intervals into delay distribution. On one hand we introduce the formalism of Duration Probabilistic Automata (DPA) supporting analysis as well as optimization. On the other hand we provide DESPEX (DEsign SPace EXplorer), a tool for performance evaluation of high-level models of applications running on multi-core platforms. We also show its usage on several case studies.

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2016-06-14T19:51:32Z No. of bitstreams: 1 HadleyMagnoDaCostaSiqueira_DISSERT.pdf: 1452990 bytes, checksum: 84d7f3a1709799f4355ce71e68b94d8b (MD5) / Approved for entry into archive by Arlan Eloi Leite Silva (eloihistoriador@yahoo.com.br) on 2016-06-15T22:22:57Z (GMT) No. of bitstreams: 1 HadleyMagnoDaCostaSiqueira_DISSERT.pdf: 1452990 bytes, checksum: 84d7f3a1709799f4355ce71e68b94d8b (MD5) / Made available in DSpace on 2016-06-15T22:22:57Z (GMT). No. of bitstreams: 1 HadleyMagnoDaCostaSiqueira_DISSERT.pdf: 1452990 bytes, checksum: 84d7f3a1709799f4355ce71e68b94d8b (MD5) Previous issue date: 2015-08-18 / O projeto de sistemas embarcados de tempo real requer um controle preciso da passagem de tempo na computa??o realizada pelos m?dulos e na comunica??o entre os mesmos. Geralmente, esses sistemas s?o constitu?dos de v?rios m?dulos, cada um projetado para uma tarefa espec?fica e com comunica??o restrita com os demais m?dulos a fim de se obter a temporiza??o necess?ria. Essa estrat?gia, chamada de arquitetura federada, j? est? se tornando invi?vel em frente as demandas atuais de custo, desempenho e qualidade exigidas dos sistema embarcados. Para atacar esse problema, atualmente se prop?e o uso de arquiteturas integradas, que consistem em um ou poucos circuitos realizando v?rias tarefas em paralelo de forma mais eficiente e com redu??o de custos. Entretanto, ? preciso garantir que a arquitetura integrada possua componibilidade temporal, ou seja, a capacidade de projetar cada tarefa temporalmente isolada das demais a fim de manter as caracter?sticas individuais de cada tarefa. As ?Precision Timed Machines? s?o uma abordagem de arquitetura integrada que advoca o uso de processadores ?multithreaded? para garantir componibilidade temporal. Dessa forma, o presente trabalho apresenta a implementa??o de uma ?Precision Timed Machine? chamada Hivek-RT. Este processador, que ? um VLIW com suporte ? ?Simultaneous Multithreading?, ? capaz de executar eficientemente tarefas de tempo real quando comparado ? um processador tradicional. Al?m da execu??o eficiente, a arquitetura facilita a implementa??o, do ponto de vista de programa??o, de tarefas de tempo real. / The real-time embedded systems design requires precise control of the passage of time in the computation performed by the modules and communication between them. Generally, these systems consist of several modules, each designed for a specific task and restricted communication with other modules in order to obtain the required timing. This strategy, called federated architecture, is already becoming unviable in front of the current demands of cost, required performance and quality of embedded system. To address this problem, it has been proposed the use of integrated architectures that consist of one or few circuits performing multiple tasks in parallel in a more efficient manner and with reduced costs. However, one has to ensure that the integrated architecture has temporal composability, ie the ability to design each task temporally isolated from the others in order to maintain the individual characteristics of each task. The Precision Timed Machines are an integrated architecture approach that makes use of multithreaded processors to ensure temporal composability. Thus, this work presents the implementation of a Precision Machine Timed named Hivek-RT. This processor which is a VLIW supporting Simultaneous Multithreading is capable of efficiently execute real-time tasks when compared to a traditional processor. In addition to the efficient implementation, the proposed architecture facilitates the implementation real-time tasks from a programming point of view.

A necessidade de aumento de produção, da redução de custos e do aumento da qualidade de bens de consumo, tem motivado a constante evolução dos sistemas de produção, migrando os tradicionais sistemas de produção para os modernos e complexos sistemas de manufatura, onde a performance depende da eficiência dos equipamentos e do controle do processo. Por outro lado, a eficiência dos equipamentos depende de sua confiabilidade e manutenabilidade. Neste trabalho a análise de performance é avaliada com o uso de Rede de Petri p-t-Temporizada e através de simulações, incluindo a avaliação da confiabilidade do processo pela análise da otimização da saída do sistema, isto é, quantidade de itens produzidos. Nesta abordagem, uma lógica linear foi desenvolvida e validada utilizando-se uma comparação de resultados das classes de estados do algoritmo proposto com a ferramenta de simulação Tina para um modelo de um esquema produtor consumidor. Apresenta-se um estudo de caso na indústria automotiva, consistindo na análise dos problemas reais enfrentados em uma fábrica de carrocerias, com o uso da Rede de Petri p-t-Temporizada. / The necessity of growing in production, with reduction of costs and improvement in the quality of consumption good, has motivated the constant evolution of production systems, transforming traditional production systems into the modern and complex manufacturing systems, where the performance depends on the efficiency of the equipment and process control. On the other hand, the equipment efficiency depends of their reliability and maintainability. In this work it is proposed a performance evaluation and analysis with the use of p-t- Timed Petri Nets using simulations, including process reliability analysis of the system through the throughput optimization, i.e., produced amount of goods. In this approach, a linear logic statement was developed and validated using a comparison of results of classes of states between the Tina simulation environment and the algorithm considered for a model of a producing consuming system. A case study in the automotive industry is presented, consisting of the analysis of the real problems found in a body shop plant, with the use of Timed Petri Net.

Many automotive systems are real-time systems, which means that not only correct operationsbut also appropriate timings are their main requirements. Considering the in uence that end-to-end delay might have on the performance of the systems, the calculation of it is of necessity.Abundant techniques have actually been proposed, and some of them have already been applied intopractical systems. In spite of this, some further work still needs to be done. The target of thisthesis is to evaluate and compare two end-to-end timing analysis methods from dierent aspectssuch as data age, consumption time, and then decide which method is a prior choice for end-to-end timing analysis. The experiments can be divided into three blocks, system generation andend-to-end delay calculation by two methods respectively. The experiments focus on two kinds ofperformance parameters, data age and the consumption time that these two methods cost duringtheir execution. By changing the system generating parameters like task number and periods, thechanges of performances of the two methods are analyzed. The performances of the two dierentmethods are also compared when they are applied into the same automotive systems. According tothe results of the experiments, the second method can calculate more accurate data age and consumeless time than the rst method does.