La réduction des dimensions et paramètres électriques des transistors, fruit des progrès dans les technologies de fabrication de circuits intégrés, rend les composants présents et futurs de plus en plus sensibles aux perturbations appelées évènements singuliers S.E.E. (Single Event Effects). Ces événements sont la conséquence d'une impulsion de courant résultant de l'impact dans des zones sensibles du circuit, de particules énergétiques présentes dans l'environnement dans lequel ils fonctionnent. Parmi les différents types de SEE, peuvent être mentionnés les SEU (Single Event Upsets) qui consistent en l'inversion du contenu de cellules mémoires, les SEL (Single Event Latchups) qui donnent lieu à des courts-circuits masse-alimentation et peuvent donc conduire à la destruction du circuit par effet thermique. Cette thèse a pour but de décrire et valider les méthodologies nécessaires pour évaluer de manière précise la sensibilité face aux radiations de deux types de circuits numériques représentatifs, processeurs et mémoires, composants utilisés dans la plupart des systèmes embarqués.

Avec l'accroissement de la complexité des traitements effectués à bord des véhicules spatiaux et l'utilisation de circuits de plus en plus intégrés, le phénomène d'upset devient de plus en plus critique. En effet, ce phénomène se traduit par le basculement intempestif du contenu d'un point mémoire suite à l'impact d'une particule lourde dans des zones sensibles du circuit. Ses conséquences sont parfois fatales et peuvent conduire à la perte voire à la destruction de l'engin sur lequel il a eu lieu. Les réseaux de neurones artificiels constituent une nouvelle approche de traitement de l'information. Ils offrent des solutions compactes et rapides pour une large gamme de problèmes, en particulier ceux ayant des contraintes temps réel tel le cas de la plupart des applications spatiales actuelles. Ceci est davantage vrai avec l'utilisation des émulations et des implantations matérielle. Parmi les propriétés importantes des réseaux de neurones, on peut citer leur tolérance aux fautes qui mesure leur aptitude à exécuter la tâche qui leur est demandée en présence d'informations erronées et de maintenir leur capacité de calcul même si une partie du réseau est endommagée. L'objectif de cette thèse est d'étudier la tolérance aux fautes des réseaux de neurones face aux fautes de type upset et ceci en vue d'étudier la possibilité de leur utilisation, sous forme matérielle, dans un environnement radiatif tel que l'espace, le but étant de choisir parmi des circuits candidats, ceux qui sont acceptés (ou rejetés) pour des applications spatiales. Pour ce faire, plusieurs réseaux et plusieurs circuits ont été testés. Les expériences réalisées étaient de type simulation logicielle d'erreurs, injection matérielle de fautes et tests aux ions lourds. Les résultats obtenus montrent que les réseaux de neurones artificiels sont tolérants aux fautes de type upsets ce qui en fait un bon candidat pour les applications s'exécutant à bord des engins spatiaux.

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

abstract: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

Cette thèse s'intéresse en premier lieu à l'analyse des effetsfonctionnels des erreurs dans laconfiguration de FPGAs à base de SRAM. Ces erreurs peuvent provenir deperturbations naturelles(rayonnements, particules) ou d'attaques volontaires, par exemple avecun laser. La famille Virtex IIde Xilinx est utilisée comme premier cas pratique d'expérimentation,puis une comparaison est réaliséeavec la famille AT40K de chez ATMEL. Ceci a permis de mieux comprendrel'impact réel dedifférentes sources de perturbations, et les motifs d'erreur devantréellement être pris en compte pouraméliorer la robustesse d'un circuit implanté sur ce type detechnologie. Cette étude a nécessité ledéveloppement d'outils de conception spécifiques, permettantd'automatiser les analyses. Uneméthodologie innovante est proposée pour l'évaluation de lasensibilité de la mémoire de configurationaux SEUs : une classification des bits de configuration est établie enfonction des effets produits parleur inversion sur le fonctionnement normal de l'application. Cecipermet de déterminer les zones lesplus critiques, autorisant le développement de stratégies deprotection sélectives et à faible coût. / This thesis deals primarily with the analysis of the functionaleffects of errors in the configuration ofSRAM-based FPGAs. These errors can be due either to naturalperturbations (radiations, particles) orto malicious attacks, for example with a laser. The Xilinx Virtex IIfamily is used as first case study,then a comparison is made with the ATMEL AT40K family. This workallowed us a betterunderstanding of the real impact of perturbations, and of the errorpatterns that need to be taken intoaccount when improving the robustness of a circuit implemented on thistype of technology. Thisstudy required the development of specific design tools to automatethe analyses. An innovativemethodology is proposed for the evaluation of the configuration memorysensitivity to SEUs: aclassification of configuration bits is made with respect to theeffects produced on the application by asingle bit-flip. This enables us to identify the most critical areas,and to propose selective hardeningsolutions, improving the global reliability of the application at low cost.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

Radiation effects encountered in space or aviation environments can affect the configuration bits in Field Programmable Gate Arrays (FPGA) causing errors in FPGA output. One method of increasing FPGA reliability in radiation environments includes adding redundant logic to mask errors and allow time for repair. Despite the redundancy added with triple modular redundancy (TMR) and configuration scrubbing there exist some configuration bits that individually affect multiple TMR domains causing errors in FPGA output. A new tool called DeBit is introduced that identifies hardware resources associated with a single bit failure. This tool identifies a novel failure mode involving global routing resources and the failure mode is verified through a series of directed tests on global routing resources. Lastly, a mitigation strategy is proposed and tested on a single error in a triple modular redundancy (TMR) design.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第18411号 / 情博第526号 / 新制||情||93(附属図書館) / 31269 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 髙木 直史, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

The overall hypothesis of this work is that the physiological microbial stress response could serve as a rapid, sensitive, and mechanistically-based indicator of process upset in biological wastewater treatment systems that receive sporadic shock loads of toxic chemicals. The microbial stress response is a set of conserved and unique biochemical mechanisms that an organism activates or induces under adverse conditions, specifically for the protection of cellular components or the repair of damaged macromolecules. Using traditional immunochemical analysis techniques, the heat shock protein, GroEL, was found to be induced in activated sludge cultures exposed to perturbations of chemicals at all concentrations tested (cadmium, pentachlorophenol, and acetone) or heat stress. As total cadmium concentrations increased above 5 mg/L, there was a significant and consistent increase in effluent volatile suspended solids concentrations from activated sludge sequencing batch reactors relative to unstressed controls, but there was no additional increase in GroEL levels. Stress proteins may serve as sensitive and rapid indicators of mixed liquor toxicity which can adversely impact treatment process performance, but GroEL may not be a good candidate protein for this purpose due to the lack of a dose/response relationship. Additionally, production of stress proteins did not explain the significant deflocculation upsets that were characteristic of many of the industrially-relevant chemicals tested, including pentachlorophenol and cadmium. Although the purpose of stress response mechanisms is protective at the cellular level, the effect may be disruptive at the macroscopic level in engineered bioreactor systems. The goal of the second research phase was to determine whether the bacterial glutathione-gated, electrophile-induced potassium efflux system is responsible for deflocculation observed due to shock loads of toxic electrophilic (thiol reactive) chemicals. The results indicate significant K+ efflux from the activated sludge floc structure to the bulk liquid in response to shock loads of 1-chloro-2,4-dinitrobenzene (CDNB), N-ethylmaleimide (NEM), 2,4-dinitrotoluene (DNT), 1,4-benzoquinone (BQ), and Cd2+ to a bench-scale sequencing batch reactor (SBR) system. In most cases, the stressor chemicals caused significant deflocculation, as measured by an increase in effluent volatile suspended solids (VSS), at concentrations much less than that required to reduce the maximum specific oxygen uptake rate by 50% (IC50). This suggests that electrophile-induced activated sludge deflocculation is caused by a protective bacterial stress mechanism (as hypothesized) and that the upset event may not be detectable by aerobic respirometry. More importantly, the amount of K+ efflux appeared to correlate well with the degree of deflocculation. The transport of other cations including sodium, calcium, magnesium, iron, and aluminum, either to or from the floc structure, was negligible as compared to K+ efflux. In bench-scale SBRs, it was also determined that the K+ efflux occurred immediately (within minutes) after toxin addition and then was followed by an increase in effluent turbidity. K+ efflux and deflocculation responses were similar for bench-scale SBRs and continuous-flow reactor systems, indicating that the periods of elevated exogenous substrate levels typical in SBR systems are not required to activate electrophile-induced K+ efflux or deflocculation. This also suggests that the initial and rapid efflux of K+ immediately following electrophile addition is the factor that leads to deflocculation, not the increase in bulk liquid K+. Sphingomonas capsulata, a bacterium consistent with that found in biological wastewater treatment systems, Escherichia coli K-12, and activated sludge cultures exhibited very similar dynamic efflux/uptake/efflux responses due to the electrophilic stressors, NEM and CDNB, and the thiol reducing agent, dithiothreitol (DTT). The polyether ionophore antibiotic, nigericin, was used to artificially stimulate K+ efflux from S. capsulata and activated sludge cultures. Thus, glutathione-gated K+ efflux (GGKE) activity may cause K+ release from the cytoplasm of activated sludge bacteria into the floc structure and extracellular polymeric substances (EPS) and then diffusion-limited transport into the bulk liquid. It was not possible to resolve the effect of the GGKE system on changes in bulk liquid or floc-associated pH. However, calculations indicate that the localized K+ concentration within the floc structure immediately after chemical stress is consistent with that known to induce floc disruption as a result of KCl addition. Using alkaline phosphatase as a periplasmic marker as well as fluorescent membrane-permeable and impermeable nucleic acid stains, it was determined that a negligible amount of the K+ efflux response was due to lysis of activated sludge microorganisms. The current results are very promising and are the first to suggest that activated sludge upset (i.e. deflocculation) may be caused by a specific protective stress response in bacteria. / Ph. D.

Este trabalho consiste no estudo e análise da suscetibilidade a efeitos da radiação em projetos de circuitos gerados por ferramenta de Síntese de Alto Nível para FPGAs (Field Programmable Gate Array), ou seja, circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SOC). Através de um injetor de falhas por emulação usando o ICAP (Internal Configuration Access Port) localizado dentro do FPGA é possível injetar falhas simples ou acumuladas do tipo SEU (Single Event Upset), definidas como perturbações que podem afetar o funcionamento correto do dispositivo através da inversão de um bit por uma partícula carregada. SEU está dentro da classificação de SEEs (Single Event Effects), efeitos transitórios em tradução livre, podem ocorrer devido a penetração de partículas de alta energia do espaço e do sol (raios cósmicos e solares) na atmosfera da Terra que colidem com átomos de nitrogênio e oxigênio resultando na produção de partículas carregadas, na grande maioria nêutrons. Dentro deste contexto além de analisar a suscetibilidade de projetos gerados por ferramenta de Síntese de Alto Nível, torna-se relevante o estudo de técnicas de redundância como TMR (Triple Modular Redundance) para detecção, correção de erros e comparação com projetos desprotegidos verificando a confiabilidade. Os resultados mostram que no modo de injeção de falhas simples os projetos com redundância TMR demonstram ser efetivos. Na injeção de falhas acumuladas o projeto com múltiplos canais apresentou melhor confiabilidade do que o projeto desprotegido e com redundância de canal simples, tolerando um maior número de falhas antes de ter seu funcionamento comprometido. / This work consists of the study and analysis of the susceptibility to effects of radiation in circuits projects generated by High Level Synthesis tool for FPGAs Field Programmable Gate Array (FPGAs), that is, system-on-chip (SOC). Through an emulation fault injector using ICAP (Internal Configuration Access Port), located inside the FPGA, it is possible to inject single or accumulated failures of the type SEU (Single Event Upset), defined as disturbances that can affect the correct functioning of the device through the inversion of a bit by a charged particle. SEU is within the classification of SEEs (Single Event Effects), can occur due to the penetration of high energy particles from space and from the sun (cosmic and solar rays) in the Earth's atmosphere that collide with atoms of nitrogen and oxygen resulting in the production of charged particles, most of them neutrons. In this context, in addition to analyzing the susceptibility of projects generated by a High Level Synthesis tool, it becomes relevant to study redundancy techniques such as TMR (Triple Modular Redundancy) for detection, correction of errors and comparison with unprotected projects verifying the reliability. The results show that in the simple fault injection mode TMR redundant projects prove to be effective. In the case of accumulated fault injection, the multichannel design presented better reliability than the unprotected design and with single channel redundancy, tolerating a greater number of failures before its operation was compromised.