Este trabalho estuda os efeitos da radiação em dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays) e técnicas de proteção que podem ser aplicadas para mitigar tais efeitos. Circuitos operando no espaço ou em altitudes elevadas, como, por exemplo, em satélites e aeronaves, recebem doses de radiação e impacto de íons e outras partículas que, dependendo da altitude e de características do próprio circuito, podem afetar o seu correto funcionamento. Os FPAAs proporcionam características interessantes aos sistemas analógicos e de sinal misto, como a prototipação rápida e a possibilidade de reconfiguração dinâmica (permitindo a implementação de sistemas de instrumentação e controle adaptativos). Assim, os FPAAs podem ser atrativos aos projetistas de sistemas de aplicação espacial, uma vez que a utilização de componentes comerciais, (COTS - do inglês, Commercial Off-The-Shelf), é uma alternativa para redução de custos do sistema final. Por isso, é necessário classificar estes dispositivos segundo o nível de tolerância à radiação e desenvolver técnicas de proteção contra seus efeitos. Essencialmente, é possível dividir os efeitos da radiação em dois principais grupos: efeitos de dose total ionizante ou TID (do inglês, Total Ionizing Dose) e os eventos singulares (Single Event Effects ou SEEs). Os dois principais eventos singulares que podem perturbar os FPAAs são investigados: os SETs (Single Event Transients) e os SEUs (Single Event Upsets). Os SETs podem gerar pulsos transientes em determinados nós do circuito, e, quando atingem o inversor de controle das portas de transmissão dos bancos de capacitores do dispositivo, podem ocasionar uma redistribuição de carga entre os capacitores do banco, afetando temporariamente o sinal que trafega pelo FPAA. Tais efeitos foram investigados através de simulações spice. Já os SEUs podem afetar os FPAAs que são baseados em memória do tipo SRAM. Para investigar tais efeitos foram realizados experimentos de injeção de falhas do tipo bit-flip (inversão de bit) no bitstream de programação de um FPAA baseado neste tipo de memória. Os experimentos mostraram que a inversão de um único bit pode ser catastrófica para o funcionamento do sistema. Posteriormente, um esquema self-checking (autoverificável) baseado em redundância foi proposto. Tal esquema foi construído com os recursos programáveis do FPAA e é capaz de recuperar os dados originais de programação do dispositivo se um erro for detectado. A capacidade do esquema proposto de detectar desvios funcionais no bloco sob teste e sua confiabilidade quando os seus próprios blocos são afetados por inversão de bits de memória, foram investigadas. Finalmente, os efeitos de dose total sobre dispositivos programáveis foram investigados através de um experimento prático, no qual um FPAA comercial foi bombardeado por radiação gama proveniente de uma fonte de Cobalto-60. Os resultados experimentais mostraramm que as chaves analógicas, que proporcionam a programabilidade do dispositivo, e seus circuitos de controle são os principais responsáveis por degradar o sinal processado pelo FPAA quando determinados níveis de dose total acumulada são atingidos. / In this work the radiation effects on Field Programmable Analog Arrays (FPAAs) are studied and mitigation techniques are proposed. The main effects induced by radiation sources in electronic circuits operating in space and at high altitudes are SEU (Single Event Upset), SET (Single Event Transient) and TID (Total Ionizing Dose). FPAAs are programmable analog circuits that provide design flexibility and some interesting features for applications such as adaptive control and instrumentation and evolvable analog hardware. These features can be very useful in avionics and space applications, where the system environmental variables can vary significantly in few minutes, being necessary to re-calibrate the sensor conditioning circuits to correct errors or improve system performance, for example. Since the use of commercial off-the-shelf (COTS) components may reduce systems costs in such critical applications, it is very important to develop system-level mitigation techniques (to radiation effects), aiming the increasing of the reliability of commercial available devices (including FPAAs). Some FPAA models are based on SRAM memory cells, which make this kind of device vulnerable to SEU when employed in applications susceptible to radiation incidence. An SEU can affect the programming memory of the FPAA and change the device configuration, modifying the analog circuit behavior. In this work, fault injection experiments were performed in order to investigate the effects of SEU in a commercial FPAA by injecting bit-flips in the FPAA programming bitstream. Then, a self-checking scheme was proposed. This scheme, which is built with the FPAA available programming resources, is able to restore the original programming data if an error is detected. Fault injection was also performed to investigate the reliability of the checker when the bitstream section which controls its own blocks is corrupted due to an SEU. Results indicated a very low aliasing probability due to single faults in the checker (0.24%). Effects of SET were also studied, considering the disturbance of the switches (transmission gates) of the FPAA programmable capacitor banks. Spice simulations showed that transient pulses in the control circuit of the switches may lead to charge redistribution between the capacitors of the bank, affecting the voltage and current of the involved nodes. Finally, total ionizing dose (TID) effects were investigated by means of an irradiation experiment. In such experiment the FPAA was exposed to Cobalt-60 gamma radiation. The experimental results showed that the analog switches of the device as well as their control circuits are the main responsible for degradating the processed signal when certain radiation levels were achieved.

Cette thèse a pour objet l'étude des éléments radioactifs qui peuvent altérer le bon fonctionnement des composants électroniques au niveau terrestre. Ces éléments radioactifs sont appelés émetteurs alpha. Intrinsèques aux composants électroniques, ils se désintègrent et émettent des particules alpha qui ionisent la matière du dispositif électronique et déclenchent des SEU (Single Event Upset). Ces travaux visent à évaluer la fiabilité des circuits digitaux due à cette contrainte radiative interne aux composants électroniques. Dans ce but, tous les émetteurs alpha naturelles ou artificielles susceptibles de contaminer les matériaux des circuits digitaux ont été identifiés et classés en deux catégories : les impuretés naturelles et les radionucléides introduits. Les impuretés naturelles proviennent d'une contamination naturelle ou involontaire des matériaux utilisés. Afin d'évaluer leurs effets sur la fiabilité, le SER (Soft Error Rate) a été déterminé par simulations Monte-Carlo pour différents nœuds technologiques dans le cas de l'équilibre séculaire. Par ailleurs, avec la miniaturisation des circuits digitaux, de nouveaux éléments chimiques ont été suggérés ou employés dans la nanoélectronique. Les radionucléides introduits regroupent ce type d'élément naturellement constitué d'émetteurs alpha. Des études basées sur des simulations Monte-Carlo et des applications analytiques ont été effectués pour évaluer la fiabilité des dispositifs électroniques. Par la suite, des recommandations ont été proposées sur l'emploi de nouveaux éléments chimiques dans la nanotechnologie. / This work studies radioactive elements that can affect the proper functioning of electronic components at ground level. These radioactive elements are called alpha emitters. Intrinsic to electronic components, they decay and emit alpha particles which ionize the material of the electronic device and trigger SEU (Single Event Upset).This thesis aims to assess the reliability of digital circuits due to this internal radiative constraint of electronic components. For that, all alpha-emitting natural or artificial isotopes that can contaminate digital circuits have been identified and classified into two categories: natural impurities and introduced radionuclides.Natural impurities result from a natural or accidental contamination of materials used in nanotechnology. To assess their effects on reliability, the SER (Soft Error Rate) was determined by Monte Carlo simulations for different technology nodes in the case of secular equilibrium. Besides, a new analytical approach was developed to determine the consequences of secular disequilibrium on the reliability of digital circuits.Moreover, with the miniaturization of digital circuits, new chemical elements have been suggested or used in nanoelectronics. The introduced radionuclides include this type of element consisting of natural alpha emitters. Studies based on Monte Carlo simulations and analytical approches have been conducted to evaluate the reliability of electronic devices. Subsequently, recommendations were proposed on the use of new chemical elements in nanotechnology.

FPGAs are frequently used in network systems to provide the performance and flexibility that is required of modern computer networks while allowing network vendors to bring products to market quickly. Like all electronic devices, FPGAs are vulnerable to ionizing radiation which can cause applications operating on an FPGA to fail. These low-level failures can have a wide range of negative effects on the performance of a network system. As computer networks play a larger role in modern society, it becomes increasingly important that these soft errors are addressed in the design of network systems.This work presents a framework for testing the soft-error reliability of FPGA-based networking systems. The framework consists of the NetFPGA development board, a custom traffic generator, and a custom high-speed JTAG configuration device. The NetFPGA development board is versatile and can be used to implement a wide range of network applications. The traffic generator is used to exercise the network system on the NetFPGA and to determine the health of that system. The JTAG configuration device is used to manage reliability experiments, to perform fault injection into the FPGA, and to monitor the NetFPGA during radiation tests.This thesis includes soft-error reliability tests that were performed on an Ethernet switch network system. Using both fault injection and accelerate radiation testing, the soft error sensitivity of the Ethernet switch was measured. The Ethernet switch design was then mitigated using triple module redundancy and duplication with compare. These mitigated designs were also tested and compared against the baseline design. Radiation testing shows that TMR provides a 5.05x improvement in reliability over the baseline design. DWC provides a 5.22x improvement in detectability over the baseline design without reducing the reliability of the system.

Artificial neural networks (ANNs) are used in many types of computing applications. Traditionally, ANNs have been implemented in software, executing on CPUs and even GPUs, which capitalize on the parallelizable nature of ANNs. More recently, FPGAs have become a target platform for ANN implementations due to their relatively low cost, low power, and flexibility. Some safety-critical applications could benefit from ANNs, but these applications require a certain level of reliability. SRAM-based FPGAs are sensitive to single-event upsets (SEUs), which can lead to faults and errors in execution. However there are techniques that can mask such SEUs and thereby improve the overall design reliability. This thesis evaluates the SEU reliability of neural networks implemented in SRAM-based FPGAs and investigates mitigation techniques against upsets for two case studies. The first was based on the LeNet-5 convolutional neural network and was used to test an implementation with both fault injection and neutron radiation experiments, demonstrating that our fault injection experiments could accurately evaluate SEU reliability of the networks. SEU reliability was improved by selectively applying TMR to the most critical layers of the design, achieving a 35% improvement reliability at an increase in 6.6% resources. The second was an existing neural network called BNN-PYNQ. While the base design was more sensitive to upsets than the CNN previous tested, the TMR technique improved the reliability by approximately 7× in fault injection experiments.

Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA's configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets.Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA's configuration memory. Configuration scrubbing periodically monitors an FPGA's configuration memory utilizing mechanisms such as Error Correction Codes (ECCs), Cyclic Redundancy Checks (CRCs), a protected golden file, and partial reconfiguration to detect and correct upset memory bits. This work presents improved Xilinx 7-Series configuration scrubbing architectures that achieve minimal hardware footprints, competitive performance metrics, and robust detection and correction capabilities. The two principal scrubbing architectures presented in this work are the readback and hybrid scrubbers which detect and correct Single Bit Upsets (SBUs) and Multi-Bit Upsets (MBUs). Harnessing the performance advantages granted by the 7-Series internal Readback CRC scan, a hybrid scrubber built in software for the Zynq XZC07020 FPGA has been measured to correct SBUs in 8.024 ms, even-numbered MBUs in 13.38 ms, and odd-numbered MBUs in 21.40 ms. It can also perform a full readback scrub of the entire device in under two seconds. These scrubbing architectures were validated in radiation beam tests, where one of the architectures corrected MBUs as large as sixteen bits in a single frame.

A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross section for specific FPGA designs. The results of this radiation testing were then analyzed and compared with similar fault injection tests, with results suggesting that the fault injection tool behavior is indeed accurate and valid. The fault injection tool can be used to determine the sensitivity of an FPGA design to configuration memory upsets. Additionally, fault mitigation techniques designed to increase the reliability of an FPGA design in spite of upsets within the configuration memory, can be thoroughly tested through fault injection. Fault injection testing should help to increase the feasibility of reconfigurable computing in space. FPGAs are well suited to the computational demands of space based signal processing applications; however, without appropriate mitigation or redundancy techniques, FPGAs are unreliable in a radiation environment. Because the fault injection tool has been shown to reliably model the effects of single event upsets within the configuration memory, it can be used to accurately evaluate the effectiveness of fault tolerance techniques in FPGAs.

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on field-programmable gate array(FPGA)-based circuits. It analyzes and quantifies a special case in data communication, that is, the synchronization issue of signals when they are sent across clock domains in triple modular redundancy (TMR) circuits with the presence of SEUs. After demonstrating that synchronizing errors cannot be eliminated in such case, this dissertation continues to present novel synchronizer designs that can guarantee reliable synchronization of triplicated signals. Fault injection tests then show that the proposed synchronizers provide between 6 and 10 orders of magnitude longer mean time to failure (MTTF) than unmitigated synchronizers. This dissertation also studies the reliability of block random access memory (BRAM) on FPGAs. By investigating several previous reliability models for single-error correction/double-error detection (SEC/DED) memory with scrubbing, this dissertation proposes two novel MTTF models that are suitable for FPGA applications. The first one considers non-uniform write rates for probabilistic write scrubbing, and the second one combines deterministic scrubbing and probabilistic scrubbing into a single model. The proposed models reveal the impact of memory access patterns on the reliability of BRAMs. Monte Carlo simulations then demonstrate the correctness of the proposed models. At last, the memory access patterns of a type of FPGA application, digital signal processing (DSP) is studied, and mitigation mechanisms for DSP applications are discussed.

Deep learning is replacing many traditional data processing methods in computer vision, speech recognition, natural language processing and many more diverse end applications. Until only a few years ago, using deep learning networks for inference required large amount of computational resources such as memory, processing power and energy. It was not trivial to deploy the computationally-expensive deep neural networks on embedded devices with limited capabilities. In recent years however, deep learning is finding its way through the world of embedded devices. Embedded systems such as Internet of Things (IoT) devices, phones and even components in cars are being equipped with deep neural networks. This raises interesting challenges for both embedded designers and deep learning scientists to close the gap between these two domains. In this thesis work, some challenges involved in deploying deep learning for embedded systems were discussed, as well as some of the available solutions and frameworks. Moreover, focusing on the safety and fault-tolerance aspects of embedded systems, tolerance of deep neural networks against faults was investigated using an experiment-based research strategy. A fault injection framework was designed and implemented that targeted deep neural networks defined using PyTorch. The framework developed was used to perform fault injection experiments on a small deep learning network. It was found how faults have various impacts on the accuracy of the neural network depending on the type of layer targeted by the faults. Worst-case faults were identified and several architectural modifications on the deep neural network were examined to improve the fault tolerance of the neural network under study. / Djupinlärning ersätter många traditionella databehandlingsmetoder inom datorseende, röstigenkänning, språkteknologi och flera olika slutanvändningar. Fram tills några år sedan har användningen av djupinlärningsnätverk för inferens krävt stora mängder beräkningsresurser såsom minne, processorkraft och energi. Det är inte trivialt att distribuera det beräknings-dyra djupa neurala nätverket på inbyggda enheter med begränsad kapacitet. Under de senaste åren har dock djupinlärning nått världens inbyggda enheter. Inbyggda system som Internet of Things (IoT) -enheter, telefoner och till och med komponenter i bilar utrustas med djupa neurala nätverk. Detta medför intressanta utmaningar för både designers av inbyggda system och djupinlärningsforskare att minska klyftan mellan dessa två domäner. I detta examensarbete diskuteras några av utmaningarna med att distribuera djupinlärning för inbyggda system, samt tillgängliga lösningar och ramverk. Djupa neurala nätverks feltolerans undersöks. Ett ramverk för felinjicering skapades som riktade sig mot djupa neurala nätverk som använder sig av Pytorch. Ramverket användes sedan för att utföra felinjektionsexperiment på ett mindre djupinlärningsnätverk. Man kunde se hur felinjiceringar påverkade nätverkets noggrannhet på olika sätt beroende på vilket lager av nätverket felinjiceringen gjordes på. Den värsta sortens felinjicering identifierades och olika arkitektoniska modifieringar av det djupa neurala nätverket undersöktes för att förbättra feltoleransen av nätverket.

La miniaturisation des circuits intégrés numériques tend à augmenter leur sensibilité aux radiations. Ainsi le rayonnement naturel peut induire des événements singuliers et porter atteinte à la fiabilité des circuits.Cette thèse porte sur la modélisation des mécanismes à l'origine de ces événements singuliers et sur le développement de solutions de durcissement par conception permettant de limiter l'impact des radiations sur le taux d'erreur.Dans une première partie, nous avons notamment développé une approche dénommée RWDD (Random-Walk Drift- Diffusion) modélisant le transport et la collection de charges au sein d'un circuit, sur la base d'équations physiques sans paramètre d'ajustement. Ce modèle particulaire et sa résolution numérique transitoire permettent de coupler le transport des charges avec un simulateur circuit, tenant ainsi compte de l'évolution temporelle des champs électriques dans la structure. Le modèle RWDD a été intégré avec succès dans une plateforme de simulation capable d'estimer la réponse d'un circuit suite à l'impact d'une particule ionisante.Dans une seconde partie, des solutions de durcissement permettant de limiter l'impact des radiations sur la fiabilité des circuits ont été développées. A l'échelle des cellules élémentaires, de nouvelles bascules robustes aux radiations ont été proposées, en limitant leur impact les performances. Au niveau système, une méthodologie de duplication de l'arbre d'horloge a été développée. Enfin, un flot de triplication a été conçu pour les systèmes dont la fiabilité est critique. L'ensemble de ces solutions a été implémenté en technologie 65 nm et UTBB-FDSOI 28 nm et leur efficacité vérifiée expérimentalement. / The extreme technology scaling of digital circuits leads to increase their sensitivity to ionizing radiation, whether in spatial or terrestrial environments. Natural radiation can now induce single event effects in deca-nanometer circuits and impact their reliability.This thesis focuses on the modeling of single event mechanisms and the development of hardening by design solutions that mitigate radiation threat on the circuit error rate.In a first part of this work, we have developed a physical model for both the transport and collection of radiation-induced charges in a biased circuit, derived from pure physics-based equations without any fitting parameter. This model is called Random-Walk Drift-Diffusion (RWDD). This particle-level model and its numerical transient solving allows the coupling of the charge collection process with a circuit simulator, taking into account the time variations of the electrical fields in the structure. The RWDD model is able to simulate the behavior of a circuit following a radiation impact, independently of the implemented function and the considered technology.In a second part of our work, hardening solutions that limit radiation impacts on circuit reliability have been developed. At elementary cell level, new radiation-hardened latch architectures have been proposed, with a limited impact on performances. At system level, a clock tree duplication methodology has been proposed, leaning on specific latches. Finally, a triplication flow has been design for critical applications. All these solutions have been implemented in 65 nm and UTBB-FDSOI 28nm technologies and radiation test have been performed to measure their hardening efficiency.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.