Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.

Nuclear particles hitting the silicon in a electronic device can cause a change in the data in a memory bit cell or in a flip-flop. The device is still working, but the data is corrupted and this is called a soft error. A soft error caused by a single nuclear particle is called a single event upset and is a growing problem. Research is ongoing at Saab aiming at how susceptible random access memories are to protons and neutrons. This thesis describes the development of equipment for measuring cosmic-ray effects on DRAM in laboratories. The system is built on existing hardware with a FPGA as the core unit. A short history of soft errors is also given and what causes it. How a DRAM works and basic operation is explained and the difference between a SRAM. The result is a working system ready to be used.

Esse trabalho consiste no estudo e desenvolvimento de técnicas de proteção a falhas transientes, também chamadas single event upset (SEU), em circuitos programáveis customizáveis por células SRAM. Os projetistas de circuitos eletrônicos estão cada vez mais predispostos a utilizar circuitos programáveis, conhecidos como Field Programmable Gate Array (FPGA), para aplicações espaciais devido a sua alta flexibilidade lógica, alto desempenho, baixo custo no desenvolvimento, rapidez na prototipação e principalmente pela reconfigurabilidade. Em particular, FPGAs customizados por SRAM são muito importantes para missões espaciais pois podem ser rapidamente reprogramados à distância quantas vezes for necessário. A técnica de proteção baseada em redundância tripla, conhecida como TMR, é comumente utilizada em circuitos integrados de aplicações específicas e pode também ser aplicada em circuitos programáveis como FPGAs. A técnica TMR foi testada no FPGA Virtex® da Xilinx em aplicações como contadores e micro-controladores. Falhas foram injetadas em todos as partes sensíveis da arquitetura e seus efeitos foram detalhadamente analisados. Os resultados de injeção de falhas e dos experimentos sob radiação em laboratório comprovaram a eficácia do TMR em proteger circuitos sintetizados em FPGAs customizados por SRAM. Todavia, essa técnica possui algumas limitações como aumento em área, uso de três vezes mais pinos de entrada e saída (E/S) e conseqüentemente, aumento na dissipação de potência. Com o objetivo de reduzir custos no TMR e melhorar a confiabilidade, uma técnica inovadora de tolerância a falhas para FPGAs customizados por SRAM foi desenvolvida para ser implementada em alto nível, sem modificações na arquitetura do componente. Essa técnica combina redundância espacial e temporal para reduzir custos e assegurar confiabilidade. Ela é baseada em duplicação com um circuito comparador e um bloco de detecção concorrente de falhas. Esta nova técnica proposta neste trabalho foi especificamente projetada para tratar o efeito de falhas transientes em blocos combinacionais e seqüenciais na arquitetura reconfigurável, reduzir o uso de pinos de E/S, área e dissipação de potência. A metodologia foi validada por injeção de falhas emuladas em uma placa de prototipação. O trabalho mostra uma comparação nos resultados de cobertura de falhas, área e desempenho entre as técnicas apresentadas. / This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Esta pesquisa teve como objetivo investigar que concepções os professores da Educação Especial têm sobre seus alunos, e que características e funcionalidade atribuem a suas práticas e a seus educandos com transtorno autista. O enfoque de narrativas de concepções sobre práticas desenvolvidas em classe especial para alunos autistas possibilitou preencher lacunas num campo carente de pesquisas, que é o autismo no ensino especial em escola pública. Sendo o professor o enfoque central deste estudo, elegeu-se como participante uma professora que atuava em educação especial, ministrando aulas em classe especial na rede pública de ensino para quatro alunos com transtorno autista, no Município do Rio de Janeiro, na Baixada Fluminense. O estudo de caso com abordagem etnográfica foi utilizado por possibilitar um contato direto do investigador com os sujeitos da pesquisa, permitindo desvelar os significados, percepções e concepções que os participantes têm sobre suas experiências e o mundo que os cerca. Os dados foram coletados de forma descritiva a partir de observações diretas do cotidiano escolar, do registro em gravações em vídeo e áudio, de entrevistas semi-estruturadas ou livres, bem como da análise de documentos, com a duração de quatro meses. A análise dos dados ocorreu em etapas: transcrição, decodificação, identificação e análise utilizando como suporte o processo das triangulações de Erickson (1988), que forneceu subsídios para composição das categorias de análise e interpretações subseqüentes. A pesquisa revelou que a forma como a professora concebia seus alunos determinava suas práticas e atitudes em relação aos mesmos. No caso em estudo esta condição era expressa por uma concepção assistencialista e protecionista que vigorava em sala de aula através do oferecimento de tarefas infantilizadas a alunos jovens e adultos. Essa forma de conceber os alunos também limitava as ações dos mesmos no ambiente escolar colaborando para o desenvolvimento de relações de dependência. Os achados apontam para a importância de um planejamento estruturado em autismo e a necessidade da formação contínua do educador. / This research had as objective investigates that conceptions the teachers of the Special Education have on their students, and that characteristics and functionality attribute their practices and to their students with autistic upset. The focus of narratives of conceptions on practices developed in special class for autistic students made possible to fill out gaps in a lacking field of researches, that it is the autism in the special teaching in public school. Being the teacher the central focus of this study, it was chosen as participant a teacher that acted in special education, supplying classes in special class in the public net of teaching for four students with autistic upset, in the Municipal district of Rio de Janeiro, in the Fluminense Slope. The case study with approach ethnographic was used for making possible a direct contact of the investigator with the subject of the research, allowing to reveal the meanings, perceptions and conceptions that the participants have on their experiences and the world that it surrounds them. The data were collected in a descriptive way starting from direct observations of the daily school, of the registration in recordings in video and audio, of semi-structured interviews or liberate, as well as of the analysis of documents, with the duration of four months. The analysis of the data happened in stages: transcription, decoding, Identification and analysis using as support the process of the triangulations of Erickson (1988), that it supplied subsidies for composition of the analysis categories and subsequent interpretations.The research revealed that the form as the teacher conceived their students determined their practices and attitudes in relation to the same ones. In the case in study this condition was expressed by a assistencialist and protectionist conception that forced at classroom through the offer of tasks to become infantile the young and adult students. That form of conceiving the students also limited the actions of the same ones in the school atmosphere collaborating for the development of dependence relationships. The discoveries appear for the importance of a planning structured in autism and the need of the educator's continuous formation.

Esse trabalho consiste no estudo e desenvolvimento de técnicas de proteção a falhas transientes, também chamadas single event upset (SEU), em circuitos programáveis customizáveis por células SRAM. Os projetistas de circuitos eletrônicos estão cada vez mais predispostos a utilizar circuitos programáveis, conhecidos como Field Programmable Gate Array (FPGA), para aplicações espaciais devido a sua alta flexibilidade lógica, alto desempenho, baixo custo no desenvolvimento, rapidez na prototipação e principalmente pela reconfigurabilidade. Em particular, FPGAs customizados por SRAM são muito importantes para missões espaciais pois podem ser rapidamente reprogramados à distância quantas vezes for necessário. A técnica de proteção baseada em redundância tripla, conhecida como TMR, é comumente utilizada em circuitos integrados de aplicações específicas e pode também ser aplicada em circuitos programáveis como FPGAs. A técnica TMR foi testada no FPGA Virtex® da Xilinx em aplicações como contadores e micro-controladores. Falhas foram injetadas em todos as partes sensíveis da arquitetura e seus efeitos foram detalhadamente analisados. Os resultados de injeção de falhas e dos experimentos sob radiação em laboratório comprovaram a eficácia do TMR em proteger circuitos sintetizados em FPGAs customizados por SRAM. Todavia, essa técnica possui algumas limitações como aumento em área, uso de três vezes mais pinos de entrada e saída (E/S) e conseqüentemente, aumento na dissipação de potência. Com o objetivo de reduzir custos no TMR e melhorar a confiabilidade, uma técnica inovadora de tolerância a falhas para FPGAs customizados por SRAM foi desenvolvida para ser implementada em alto nível, sem modificações na arquitetura do componente. Essa técnica combina redundância espacial e temporal para reduzir custos e assegurar confiabilidade. Ela é baseada em duplicação com um circuito comparador e um bloco de detecção concorrente de falhas. Esta nova técnica proposta neste trabalho foi especificamente projetada para tratar o efeito de falhas transientes em blocos combinacionais e seqüenciais na arquitetura reconfigurável, reduzir o uso de pinos de E/S, área e dissipação de potência. A metodologia foi validada por injeção de falhas emuladas em uma placa de prototipação. O trabalho mostra uma comparação nos resultados de cobertura de falhas, área e desempenho entre as técnicas apresentadas. / This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / Esta pesquisa teve como objetivo investigar que concepções os professores da Educação Especial têm sobre seus alunos, e que características e funcionalidade atribuem a suas práticas e a seus educandos com transtorno autista. O enfoque de narrativas de concepções sobre práticas desenvolvidas em classe especial para alunos autistas possibilitou preencher lacunas num campo carente de pesquisas, que é o autismo no ensino especial em escola pública. Sendo o professor o enfoque central deste estudo, elegeu-se como participante uma professora que atuava em educação especial, ministrando aulas em classe especial na rede pública de ensino para quatro alunos com transtorno autista, no Município do Rio de Janeiro, na Baixada Fluminense. O estudo de caso com abordagem etnográfica foi utilizado por possibilitar um contato direto do investigador com os sujeitos da pesquisa, permitindo desvelar os significados, percepções e concepções que os participantes têm sobre suas experiências e o mundo que os cerca. Os dados foram coletados de forma descritiva a partir de observações diretas do cotidiano escolar, do registro em gravações em vídeo e áudio, de entrevistas semi-estruturadas ou livres, bem como da análise de documentos, com a duração de quatro meses. A análise dos dados ocorreu em etapas: transcrição, decodificação, identificação e análise utilizando como suporte o processo das triangulações de Erickson (1988), que forneceu subsídios para composição das categorias de análise e interpretações subseqüentes. A pesquisa revelou que a forma como a professora concebia seus alunos determinava suas práticas e atitudes em relação aos mesmos. No caso em estudo esta condição era expressa por uma concepção assistencialista e protecionista que vigorava em sala de aula através do oferecimento de tarefas infantilizadas a alunos jovens e adultos. Essa forma de conceber os alunos também limitava as ações dos mesmos no ambiente escolar colaborando para o desenvolvimento de relações de dependência. Os achados apontam para a importância de um planejamento estruturado em autismo e a necessidade da formação contínua do educador. / This research had as objective investigates that conceptions the teachers of the Special Education have on their students, and that characteristics and functionality attribute their practices and to their students with autistic upset. The focus of narratives of conceptions on practices developed in special class for autistic students made possible to fill out gaps in a lacking field of researches, that it is the autism in the special teaching in public school. Being the teacher the central focus of this study, it was chosen as participant a teacher that acted in special education, supplying classes in special class in the public net of teaching for four students with autistic upset, in the Municipal district of Rio de Janeiro, in the Fluminense Slope. The case study with approach ethnographic was used for making possible a direct contact of the investigator with the subject of the research, allowing to reveal the meanings, perceptions and conceptions that the participants have on their experiences and the world that it surrounds them. The data were collected in a descriptive way starting from direct observations of the daily school, of the registration in recordings in video and audio, of semi-structured interviews or liberate, as well as of the analysis of documents, with the duration of four months. The analysis of the data happened in stages: transcription, decoding, Identification and analysis using as support the process of the triangulations of Erickson (1988), that it supplied subsidies for composition of the analysis categories and subsequent interpretations.The research revealed that the form as the teacher conceived their students determined their practices and attitudes in relation to the same ones. In the case in study this condition was expressed by a assistencialist and protectionist conception that forced at classroom through the offer of tasks to become infantile the young and adult students. That form of conceiving the students also limited the actions of the same ones in the school atmosphere collaborating for the development of dependence relationships. The discoveries appear for the importance of a planning structured in autism and the need of the educator's continuous formation.

Esse trabalho consiste no estudo e desenvolvimento de técnicas de proteção a falhas transientes, também chamadas single event upset (SEU), em circuitos programáveis customizáveis por células SRAM. Os projetistas de circuitos eletrônicos estão cada vez mais predispostos a utilizar circuitos programáveis, conhecidos como Field Programmable Gate Array (FPGA), para aplicações espaciais devido a sua alta flexibilidade lógica, alto desempenho, baixo custo no desenvolvimento, rapidez na prototipação e principalmente pela reconfigurabilidade. Em particular, FPGAs customizados por SRAM são muito importantes para missões espaciais pois podem ser rapidamente reprogramados à distância quantas vezes for necessário. A técnica de proteção baseada em redundância tripla, conhecida como TMR, é comumente utilizada em circuitos integrados de aplicações específicas e pode também ser aplicada em circuitos programáveis como FPGAs. A técnica TMR foi testada no FPGA Virtex® da Xilinx em aplicações como contadores e micro-controladores. Falhas foram injetadas em todos as partes sensíveis da arquitetura e seus efeitos foram detalhadamente analisados. Os resultados de injeção de falhas e dos experimentos sob radiação em laboratório comprovaram a eficácia do TMR em proteger circuitos sintetizados em FPGAs customizados por SRAM. Todavia, essa técnica possui algumas limitações como aumento em área, uso de três vezes mais pinos de entrada e saída (E/S) e conseqüentemente, aumento na dissipação de potência. Com o objetivo de reduzir custos no TMR e melhorar a confiabilidade, uma técnica inovadora de tolerância a falhas para FPGAs customizados por SRAM foi desenvolvida para ser implementada em alto nível, sem modificações na arquitetura do componente. Essa técnica combina redundância espacial e temporal para reduzir custos e assegurar confiabilidade. Ela é baseada em duplicação com um circuito comparador e um bloco de detecção concorrente de falhas. Esta nova técnica proposta neste trabalho foi especificamente projetada para tratar o efeito de falhas transientes em blocos combinacionais e seqüenciais na arquitetura reconfigurável, reduzir o uso de pinos de E/S, área e dissipação de potência. A metodologia foi validada por injeção de falhas emuladas em uma placa de prototipação. O trabalho mostra uma comparação nos resultados de cobertura de falhas, área e desempenho entre as técnicas apresentadas. / This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

FPGAs are susceptible to radiation-induced effects that change the data in the configuration memory. These effects can cause the malfunction of the system. Triple modular redundancy has extensively been used to improve the circuit's cross-section. However, TMR has shown to be particularly susceptible to radiation effects that affect more than one memory cell such as Multiple Cell Upsets (MCU) or micro-Single Event Functional Interrupts (micro-SEFI). This work describes a statistical technique to extract Multi-Cell Upset (MCU) and micro-SEFI events from raw radiation upset data. The technique uses Poisson statistics to identify patterns in the data. The most common patterns are selected using Poisson statistics. The selected patterns are used to reconstruct MCU events. The results show the distribution of MCU, micro-SEFis, and single-bit upsets for several radiation tests. Additionally, the results show the MCU distribution based on the number of bits affected by the event. This work details the process of reconstructing MCU data and also the process to use these data during a fault injection campaign. The results show that by using MCU fault injection it is possible to replicate failures seen in the radiation test and even induce more failures than seen in the radiation test. This shows the importance of extracting MCUs from radiation data and use them to evaluate TMR-protected designs.

Current practices support the use of probiotic and prebiotic supplementation to improve chronic gastrointestinal distress (GID). The aim of this study was to determine the tolerance and benefits of GlutenShield (GS), a prebiotic, probiotic, and enzyme supplement, on adults with GID. Subjects (n=20) took either GS or the placebo for 30 days and completed a pre-treatment FFQ as well as a pre- and post-treatment GID questionnaire, blood draw, and stool sample. Participants consumed more total and saturated fat, and less fiber and whole grains compared to the recommended intake. A significant reduction in IgG2 was observed in the GS group (p=0.008) as well as a significant reduction in self-reported bloating (p=0.038) with no change observed to cytokines or SCFAs (p>0.05). GS was well tolerated and perceived to be beneficial; however, further research is needed to identify the specific population of GID patients who could most benefit from GS supplementation.

This study consists of three research phases. First, we developed corrective action strategies to mitigate the impact of calcium hypochlorite and cadmium pulse shocks for the Plum Island Wastewater Treatment Plant (WWTP) in Charleston, SC. The corrective action strategies were developed in consultation with industrial consultants and operational personnel from the utility. These strategies were tested using a laboratory scale system, which was constructed and operated similar to the parent facility. Two corrective actions were tested for calcium hypochlorite, while only one strategy was tested for the cadmium at the laboratory scale. This study shows that no corrective action strategies are required for an acute hypochlorite stress. This is due to the fact that hypochlorite is highly reactive and dissipates rapidly on contact with the wastewater matrix, thus causing only low level process deterioration. In fact, implementation of corrective action strategies results in greater process deterioration as compared to the non-intervention approach. The corrective action tested for cadmium stress showed potential for reducing the peak impact of the toxin and allowed for faster process recovery as compared to the unstressed control. For the second phase, the corrective actions were tested at a pilot scale facility operated at the Plum Island wastewater treatment plant. We tested two different corrective action strategies for cadmium, while only one strategy was tested for hypochlorite during the pilot scale study. Similar to the laboratory scale experiments, we conclude that no mitigative approaches are necessary for an acute hypochlorite stress. Additionally, the implementation of mitigative approaches for the pilot scale cadmium stress events resulted in greater process deterioration as compared to the non-intervention approach. In contrast to the laboratory scale experiments, theoretical effluent blending calculations showed that corrective actions may not reduce the impact of the cadmium stress. This was attributed to the lower intensity of process deterioration caused by the simulated cadmium stress. The pilot scale study shows that prior to implementing a corrective action strategy, the operator should determine the probable extent of process deterioration due to the detected chemical contaminant before deciding if a corrective action is needed. The pilot scale study also evaluated the effectiveness of current sensor technologies towards the upstream detection of influent anomalies and reliable monitoring of process performance during an upset event. Multivariate analysis on the rate of change of influent sensor signals was reliably able to detect the presence of both toxins tested during this study. For the third phase of this research, we investigated the impact of cadmium stress on the structure and function of bioreactor microbial communities. We observed significant increases in post-stress heterotrophic and autotrophic bacterial respiration rates for the bioreactors subjected to cadmium stress. The higher respiration rates were due to an increase in bacterial abundance in the cadmium stressed reactors. We were also able to show that the increase in bacterial abundance was not due to changes in community structure or due to cadmium induced deflocculation. In fact, this study demonstrates that transient cadmium stress reduces predator abundance within the activated sludge community and this reduction in predator grazing was responsible for the increase in bacterial abundance. This research highlights the importance of higher life forms, specifically eukaryotic microorganisms, in regulating bacterial community dynamics in systems undergoing chemical perturbations. / Ph. D.