A improved less area 6-bit 3.3V SAR pipelined ADC is proposed. In this work, a 3-bit ADC is designed by the improved TIQ technology and flash like SAR ADC selection scheme. With the proposed TIQ method, it cancels the reference voltage generators and the backend encoders to reduce the area cost, besides the flash-like SAR ADC selection scheme makes the ADC still operate at high speed. The new 3-bit DAC in the MDAC is completed only by MOS transistors which channel widths and lengths are only adjusted to form each DAC output-voltage levels rather than using of resisters and capacitors in voltage mode. By the method, the area of the new DAC is reduced. By combining the proposed 3-bit ADC with the proposed 3-bit MDAC, an improved 6-bit ADC with less area is designed. By the TSMC 2P4M 0.35µm CMOS process, the area of the ADC is less than 0.017mm . The work shows that the power consuming is 3.77mW, the sampling rate is 160MS/S, the DNL is 0.344, and the INL is 0.74.

The first topic of this thesis proposes an 8-bit, 20 MSample/s pipeline analog-to-digital converter (ADC). The sharing amplifiers technique is employed to reduce the overall number of the amplifiers wherein dynamic comparators are adopted to reduce the power consumption. The proposed design is implemented by 0.35 £gm CMOS technology. The simulation results show that maximum power consumption is 45 mW given a 3.3 V power supply, and the SFDR is 45 dB with a sinusoidal input at 5 MHz. The second topic is to describe a 5-bit, 2.4 MSample/s, low power analog-to-digital converter for ZigBee receiver using 868/915 MHz band. The converter uses the successive approximation architecture. By using 0.18 £gm CMOS technology, the simulation results show the worst-case power consumption is merely 449.6 £gW. The converter achieves the maximum differential nonlinearity of 0.3 LSB, the maximum integral nonlinearity of 0.5 LSB.

Analog-to-digital (A/D) and digital-to-analog (D/A) converters are important blocks in signal processing system because they provide the link between the analog world and digital systems. Compared with Nyquist-rate data converters, oversampling data converters are more desirable for modern submicron technologies with low voltage supplies. Today, all existing oversampling modulators in popular use are derived from sigma-delta modulation. Stability is the most significant problem in the sigma-delta modulator, because the ultimate accuracy is limited by stability. As the aggressiveness of the design increases, the margin of stability diminishes rapidly. This thesis presents the design and experimental results of the first prototype circuit implementation of the novel oversampling modulation scheme proposed by Dr. Takis Zourntos. This new class of oversampling modulators are theoretically stable. With less stability limitation, the new class of modulators can potentially achieve higher signal-to-noise ratio (SNR) or less power by designing the modulator more aggressively. This thesis describes the methods and procedures of how the new oversampling modulation theory is implemented into a circuit. Some novel circuit architectures are proposed in this modulator, such as a filter which can provide status outputs for the controller and realize arbitrary zeros and poles, comparators with synchronization latches to eliminate the effect of metastability, and a digital-to-analog converter (DAC) with current calibration circuits for high linearity. A third-order continuous-time oversampling modulator employing 4-bit quantization is implemented in a 0.35-µm double-poly complementary metal oxide semiconductor (CMOS) technology, with a chip area of 2150 × 2150 µm2. Simulation results show it achieves 83.7-dB peak SQNR, 90-dB dynamic range over a 500kHz input signal bandwidth, and 60 mW power consumption.

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components. / text

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El trabajo realizado en esta Tesis abarca el estudio de arquitecturas de conversores analógicodigitales y sus características particulares con el objetivo de obtener modelos adecuados, y estudiar la dinámica nolineal inherente al proceso de conversión para desarrollar compensadores eficientes. Las contribuciones de este trabajo pueden resu-mirse como se presenta a continuación. Se introduce una descripción general de las arquitecturas de conversión analó-gico-digital y las métricas de desempeño asociadas, lo que permite establecer el marco teórico necesario para el modela-do y compensación de estos sistemas. Luego, se presenta el desarrollo de un nuevo modelo de comportamiento para conversores Sigma-delta en tiempo contınuo. Este modelo permite obtener información adicional sobre el comportamiento de la dinámica nolineal de estos conversores, que resulta fundamental para la elección de una estructura adecuada de compensación y el desarrollo de un nuevo post-compensador eficiente orientado a bloques. El compensador desarrollado es una generalización de los sistemas tipo Wiener que permite múltiples dinámicas lineales precediendo una nolinealidad estática de orden N. De esta manera, se logra un alto grado de representación manteniendo el número de parámetros muy por debajo del requerido por el modelo de Volterra más gene-ral. También se presentan dos compensadores tipo Hammers-tein y Wiener en paralelo utilizando funciones PWL estáticas, logrando estructuras eficientes que permiten obtener un buen desempeño manteneniendo acotado el número de parámetros. Finalmente, se propone un esquema de compensación por post-procesamiento para ADC comerciales, donde todos los efectos no lineales dinámicos son reducidos de manera con-junta logrando una gran mejora en términos de aumento en la resolución efectiva. Dos modelos eficientes para el compen-sador son evaluados en un ADC comercial de alta resolución y velocidad, utilizando datos de entrada-salida obtenidos me-diante mediciones de laboratorio. Se realizan consideraciones adicionales sobre las señales de entrada utilizadas para entre-nar el compensador. En particular, se introduce una nueva secuencia de entrenamiento compuesta por la concatenación serial de varias señales monotonales, y se comprueba que el método es robusto ante diferencias entre la señal de entre-namiento y la señal muestreada, logrando una mejora signifi-cativa sobre el ancho de banda de Nyquist completo. / The work comprised in this Thesis addresses the study of different analog-to-digital converter architectures and their particular characteristics in order to obtain adequate models, and study the nonlinear dynamics inherent to the conversion process in order to develop efficient compensators. The main contributions of this work can be summarized as follows. A general description of traditional analog-to-digital conversion architectures is introduced along with the associated perfor-mance metrics, which is usefull to establish the theoretical background required to model and compensate these sys-tems. Then, the development of a new complete behavioral model for continuous time sigma-delta converters is presen-ted. This model allows to obtain additional information on the nonlinear dynamics of these converters, which is key for the selection of an adequate compensator structure and the development of a novel block oriented eficient postcompensa-tor. The developed compensator is a generalization of Wiener systems that allows for multiple linear dynamics preceding an Nth order nonlinearity. In this manner, a high degree of repre-sentation is achieved while keeping the amount of parameters much lower than the amount required for the more general Volterra model. Two compensators of the form of parallel Hammerstein and Wiener models using static PWL functions were also presented. The efficient structure proposed allows to obtain good performance while keeping the amount of parameters low. Finally, a compensation scheme for commer-cial ADCs by post-processing is prsented, where all nonlinear dynamic effects are jointly reduced achieving a great improve-ment in terms of effective resolution enhancement. Two effi-cient models for the compensator are evaluated in a high resolution and high conversion rate commercial ADC, using input-output data obtained by actual measurements. Additio-nal considerations are performed regarding the input signal used to train the compensator. In particular, a novel input sequence is introduced which is composed of the concatena-tion of several monotone sinusoid signals, and the method is shown to be robust to missmatches between the training and sampled signals, achieving a signifficant improvement over the whole Nyquist bandwidth.

In this thesis, the circuits are designing with TSMC.18£gm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 150MS/s and 12-bits individually. In order to achieve a high speed, low power consumption pipelined ADC. The proposed pipelined stage is replaced Flash ADC by SAR ADC and add an extra comparator to determine one additional bit in sampling phase of pipelined stage. This technique reduces large number of pipelined stage and opamp which is energy-hungry in the pipelined ADC. Second, the SAR ADC provides inherent sample-and-hold mechanism so that the front-end sample-and-hold amplifier circuit is non-need. Third, the SAR ADC can achieve rail-to-rail input signal swing and improve the conversion accuracy rather than Flash ADC. The dynamic comparator is used for lower power consumption for whole circuit. Furthermore, this pipelined ADC implement under a supply voltage as low as 1.8V. The bootstrapped switch is used for controlling the sampling in the front-end. It can reduce the impacts of linearity for operating under low supply voltage. The operation amplifier implement by the partially switched-opamp technique to reduce more power consumption. Finally, the output codes are translated by digital correction circuit, it enhance the comparators input offset error tolerance.

Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved. / text

The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out. / text

The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the design costs, etc. The functioning of an all-digital ADC is based on the time domain signal processing approach, which brings a high time resolution obtained by the use of a nanometer CMOS process. An all-digital ADC design is implemented by using a combination of the digital Voltage-Controlled Oscillator (VCO) and a Time-to-Digital Converter (TDC). The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. In addition, the VCO works as a time based quantizer. The time-based signal from the VCO output is then processed by the TDC quantizer in order to generate the digital code sequences. The fully digital VCO-based ADC has the advantage of superior time resolution. Moreover, the VCO-based ADC offers a first order noise shaping property of its quantization noise. This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter. The circuit level simulations have been done in Cadence Virtuoso ADE. A multi-phase VCO and multi-bit quantization architecture has been chosen for this 8-bit ADC. The power consumption of the ADC is approximately 630 μW at 1.0 V power supply and the figure of merit is around 410 fJ per conversion step.