Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well. In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources. In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations. The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs. Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

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<p>0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. </p><p>This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). </p><p>Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. </p><p>The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. </p><p>In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.</p>

Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice. The sampling instances have been set at 110 ps apart. In contrast to the traditional time redundancy, which requires two clock cycles to generate a given output, the SRA generates an output in a single clock cycle. The sampled sum outputs are compared using a 64-bit XOR tree to detect any possible error. An energy efficient 4-input transmission gate based XOR logic is implemented to reduce the delay and the power in this case. The pseudo-static logic (PSL), which has the ability to recover from a particle induced transient, is used in the adder implementation. In comparison with the space redundant approach which requires hardware duplication for error detection, the SRA is 50% more area efficient. The proposed SRA is simulated for different operands with errors inserted at different nodes at the inputs, the carry merge tree, and the sum generation circuit. The simulation vectors are carefully chosen such that the SET is not masked by error masking mechanisms, which are inherently present in combinational circuits. Simulation results show that the proposed SRA is capable of detecting 77% of the errors. The undetected errors primarily result when the SET causes an even number of errors and when errors occur outside the sampling window.

This final year project describes the linearisation method Cartesian feedback and the design of such a feedback with a 2.4GHz power amplifier. To investigate the functionality of the Cartesian feedback ideal blocks with no current consumption were made and then gradually analog circuits were introduced into the feedback. The Cartesian feedback design consists of a subtracter, a modulator and a preamplifier in the top path and a demodulator and a filter in the feedback path. The blocks that are discussed in this report are the subtracter and the modulator unit. The circuits are designed in a 0.35µm SiGe BiCMOS technology. The result of the Cartesian feedback showed an increase in 1dB compression point by 6.2dBm and the IMD was improved by 17dB.

0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.

Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice. The sampling instances have been set at 110 ps apart. In contrast to the traditional time redundancy, which requires two clock cycles to generate a given output, the SRA generates an output in a single clock cycle. The sampled sum outputs are compared using a 64-bit XOR tree to detect any possible error. An energy efficient 4-input transmission gate based XOR logic is implemented to reduce the delay and the power in this case. The pseudo-static logic (PSL), which has the ability to recover from a particle induced transient, is used in the adder implementation. In comparison with the space redundant approach which requires hardware duplication for error detection, the SRA is 50% more area efficient. The proposed SRA is simulated for different operands with errors inserted at different nodes at the inputs, the carry merge tree, and the sum generation circuit. The simulation vectors are carefully chosen such that the SET is not masked by error masking mechanisms, which are inherently present in combinational circuits. Simulation results show that the proposed SRA is capable of detecting 77% of the errors. The undetected errors primarily result when the SET causes an even number of errors and when errors occur outside the sampling window.

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions.

This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers. A high speed and low power 8-bit CLA using dual- Vth domino logic blocks arranged in a PLA-like style with pipelining is presented. According to parallely precharge and sequentially evaluate in a cascaded set of domino logic blocks, transistors in the precharge part and the evaluation part of dual- Vth domino logic are, respectively, replaced by high Vth transistors to reduce subthreshold leakage current through OFF transistors, and low Vth transistors. Moreover, an nMOS transistor is inserted in the precharge phase of the output inverter such that the two-phase dual- Vth domino logic can be properly applied in a pipeline structure. Consequently, the proposed design keeps the advantage of high speed while attaining the effect of low power dissipation. A low-cost digital I/Q separator is presented in the second part of this thesis. Using digital I/Q separator in place of the traditional analog I/Q separator guarantees the design conquer gain and phase mismatch problems between the I and Q channels. The proposed design can berealized by inverters and shifters such that the goal of low cost can be achieved.

<p>This final year project describes the linearisation method Cartesian feedback and the design of such a feedback with a 2.4GHz power amplifier. </p><p>To investigate the functionality of the Cartesian feedback ideal blocks with no current consumption were made and then gradually analog circuits were introduced into the feedback. The Cartesian feedback design consists of a subtracter, a modulator and a preamplifier in the top path and a demodulator and a filter in the feedback path. The blocks that are discussed in this report are the subtracter and the modulator unit. The circuits are designed in a 0.35µm SiGe BiCMOS technology. </p><p>The result of the Cartesian feedback showed an increase in 1dB compression point by 6.2dBm and the IMD was improved by 17dB.</p>