The ever-growing need for high speed data transmission is driven by multimedia and telecommunication demands. Traditional metallic media, such as copper coaxial cable, prove to be a limiting factor for high speed communications. Fiber optic methods provide a feasible solution that lacks the limitations of metallic mediums, including low bandwidth, cross talk caused by magnetic induction, and susceptibility to static and RF interferences. The first scientists to work with fibers optics started in 1970. One of the early challenges they faced was to produce glass fiber that was pure enough to be equal in performance with copper based media. Since then, the technology has advanced tremendously in terms of performance, quality, and consistency. The advancement of fiber optic communication has met its limits, not in the purity of its fiber media used to guide the data-modulated light wave, but in the conversion back and forth between electric signals to light. A high speed optic receiver must be used to convert the incident light into electrical signals. This thesis describes the design of a 2.5 GHz Optoelectronic Amplifier, the front end of an optic receiver. The discussion includes a survey of feasible topologies and an assessment of circuit techniques to enhance performance. The amplifier was designed and realized in a TSMC 0.18 µm CMOS process.

As the number of people with diabetes continues to increase, research efforts improving glucose testing methods and devices are under way to improve outcomes and quality of life for diabetic patients. This dissertation describes the design and testing of a Data Acquisition Unit (DAU) providing low noise photocurrent spectra for use in a continuous glucose monitoring system. The goal of this research is to improve the signal to noise ratio (SNR) of photocurrent measurements to increase glucose concentration measurement accuracy. The glucose monitoring system consists of a portable monitoring device and base station. The monitoring device measures near infrared (IR) absorption spectra from interstitial fluid obtained by microdialysis or ultrafiltration probe and transmits the spectra to a base station via USB or a ZigBee radio link. The base station utilizes chemometric calibration methods to calculate glucose concentration from the photocurrent spectra. Future efforts envisage credit card-sized monitoring devices. The glucose monitor system measures the optical absorbance spectrum of an interstitial fluid (ISF) sample pumped through a fluid chamber inside a glucose sensor. Infrared LEDs in the glucose sensor illuminate the ISF sample with IR light covering the 2.2 to 2.4 micron wavelength region where glucose has unique features in its absorption spectrum. Light that passes through the sample propagates through a linearly variable bandpass filter and impinges on a photodiode array. The center frequency of the variable filter is graded along its length such that the filter and photodiode array form a spectrometer. The data acquisition unit (DAU) conditions and samples photocurrent from each photodiode channel and sends the resulting photocurrent spectra to the Main Controller Unit (MCU). The MCU filters photocurrent samples providing low noise photocurrent spectra to a base station via USB or Zigbee radio link. The glucose monitoring system limit of detection (LOD) from a single glucose sensor wavelength is 5.8 mM with a system bandwidth of 0.00108 Hz. Further analysis utilizing multivariate calibration methods such as the net analyte signal method promise to reduce the glucose monitoring system LOD approaching a clinically useful level of approximately 2 mM.

<p>The purpose with the report is to show that it is possible to design a class-D amplifier, using a programmable FPGA mounted on a developing card from Xess and a H-bridge. The FPGA was programmed in VHDL which is the language the software from Xilinx use to implement a logical function into the FPGA The logical function corresponds to a modeling of the music signal and the modeling can be described as a comparator which compare the music signal with a triangle wave and as a out signal produce a pulse width modulated (PWM) signal. The report is also a review and evaluating of two different modulating technologies, AD- modeling and BD-modeling. A detailed part about how the H-bridge was designed and how it works. The result of this project is a working audio amplifier to a significant lower price than the products in todays market.</p>

The purpose with the report is to show that it is possible to design a class-D amplifier, using a programmable FPGA mounted on a developing card from Xess and a H-bridge. The FPGA was programmed in VHDL which is the language the software from Xilinx use to implement a logical function into the FPGA The logical function corresponds to a modeling of the music signal and the modeling can be described as a comparator which compare the music signal with a triangle wave and as a out signal produce a pulse width modulated (PWM) signal. The report is also a review and evaluating of two different modulating technologies, AD- modeling and BD-modeling. A detailed part about how the H-bridge was designed and how it works. The result of this project is a working audio amplifier to a significant lower price than the products in todays market.

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

In this thesis work, a 3-stage ultra broadband amplifier operating in 2-18 GHz frequency band with gain 23 dB is designed, simulated and fabricated. The amplifier is based on cascaded, reactively terminated single stage distributed amplifier (CRTSSDA) concept. The idea of including reactive terminations to achieve broadband gain is investigasted and simulated. The simulated design is fabricated and measurements of the fabricated amplifier are compared with simulation results. Also practical experience on working at high frequencies with surface mount components is presented in this thesis work.

The advancement in integrated circuit (IC) technology has resulted in scaling down of device sizes and supply voltages without proportionally scaling down the threshold voltage of the MOS transistor. This, coupled with the increasing demand for low power, portable, battery-operated electronic devices, like mobile phones, and laptops provides the impetus for further research towards achieving higher integration on chip and low power consumption. High gain, wide bandwidth amplifiers driving large capacitive loads serve as error amplifiers in low-voltage low drop out regulators in portable devices. This demands low power, low area, and frequency-compensated multistage amplifiers capable of driving large capacitive loads. The first part of the research proposes two power and area efficient frequency compensation schemes: Single Miller Capacitor Compensation (SMC) and Single Miller Capacitor Feedforward Compensation (SMFFC), for multistage amplifiers driving large capacitive loads. The designs have been implemented in a 0.5??m CMOS process. Experimental results show that the SMC and SMFFC amplifiers achieve gain-bandwidth products of 4.6MHz and 9MHz, respectively, when driving a load of 25K&#948;/120pF. Each amplifier operates from a ??1V supply, dissipates less than 0.42mW of power and occupies less than 0.02mm2 of silicon area. The inception of the latest IEEE standard like IEEE 802.16 wireless metropolitan area network (WMAN) for 10 -66 GHz range demands wide band amplifiers operating at high frequencies to serve as front-end circuits (e.g. low noise amplifier) in such receiver architectures. Devices used in cascade (multistage amplifiers) can be used to increase the gain but it is achieved at an expense of bandwidth. Distributing the capacitance associated with the input and the output of the device over a ladder structure (which is periodic), rather than considering it to be lumped can achieve an extension of bandwidth without sacrificing gain. This concept which is also known as distributed amplification has been explored in the second part of the research. This work proposes certain guidelines for the design of distributed low noise amplifiers operating at very high frequencies. Noise analysis of the distributed amplifier with real transmission lines is introduced. The analysis for gain and noise figure is verified with simulation results from a 5-stage distributed amplifier implemented in a 0.18??m CMOS process.

CMOS is the favorite candidate process for the high integration of the wireless communication IC blocks, RF frontend and digital baseband circuitry. Also the design of the RF power amplifier stage is the one of the most important part of the RF CMOS circuit design. Since high frequency and high power simultaneously exists on this stage, devices works on the limits of the process. Therefore standard device models may not be valid enough for a successful design. In the thesis high frequency passive device and MOS transistor models for the CMOS process searched though the literature and presented. Besides, different structures of the inductors are investigated for the best quality factor for the chosen process. Class E power amplifiers can reach very high efficiencies and they are very suitable for the low power applications. After the derivation of the classical Class E equations is presented, a new Class E circuit model including MOS transistor&rsquo / s channel resistance is developed and new sets of equations are obtained for the model. Circuit parameters are determined using numerical methods. Class E circuit simulations with these new parameters and earlier parameters are compared. Finally, a 100mW 2.4GHz Class E power amplifier is designed and simulated targeting Bluetooth applications. In this design, Class E circuit parameters are determined for AMS CMOS 0.35um process MOS transistor including the channel resistance. Simulations are performed using Cadence/BSIM3v3 and OrCad PSPICE.

With the ongoing push for wireless systems to accommodate more users and support higher data rates more efficient modulation schemes have been created that are more advanced than simple FM and AM modulation used for radio broadcasting. These modulation schemes, such as orthogonal frequency division multiplexing (OFDM), suffer from high peak to average power ratios. Standard Class A and Class AB amplifiers cannot simultaneously achieve good linearity and efficiency, and therefore there has been an increase in the development of new topologies to combat this issue. Common features to these circuits is power combining of two or more separate transistors. In this work, we consider various ways of two-source power combining and identify four topologies of interest. We notice that linear power-efficient amplifiers reported to date are based upon two of the identified combining strategies. We believe that no amplifiers have been reported that leverage the other two alternatives. This work produces a fully-functional amplifier based on one of these alternatives. The prototypes are intended to serve as concept verification of the architecture and hence are implemented at lower (1 MHz) frequencies.

This work deals with methods used in design of low voltage operational amplifiers. It describes some of the most commonly used methods. Properties of these methods are verified by computer simulation of operational transconductance amplifiers that are utilizing them.