I study various aspects of mutual funds in my thesis. These are divided over four chapters. The first chapter is an introduction to the thesis and sets out an executive summary of my research. The second to fourth chapters each deal with a new concept. The second chapter shows that the sensitivity of an investor's reaction to a mutual fund's recent performance increases with the fund's historical performance. Put differently, bad (good) performance combined with a good-history for a fund results in a greater fraction of capital outflows (inflows) relative to a fund with a poor past history. The evidence is puzzling as we would expect investors to stick with a fund having a good-history, even after a single bad performance. I solve this problem using a model with investors of differing attentiveness. In equilibrium, fund owner's attentiveness increases the historical record of a fund. With this mechanism, the model can explain the higher sensitivity of outflows for higher reputation funds. The chapter is important in that it shows that return-chasing behavior is not ubiquitous. It also provides a clear evidence where the market is slow to incorporate the new information into decision making. The third chapter studies the managerial side of the mutual funds industry regarding the risk-taking behavior of the mutual funds. Mutual fund managers are compared against a benchmark or with the peers. The employment, as well as investor's capital flows, depends on how the manager fares in the competition. I present new evidence in the chapter that the exposure of a manager to these risks is heterogeneous, and manager's historical performance governs it. The evidence implies that the risk-appetite and behavior of a manager depends on his historical performance. I find strong support in the data for this hypothesis. I show that funds with poor historical performance do not boost the portfolio risk to catch up with the peers if they are lagging at the interim date. In general, the risk appetite of the poor-history manager is less driven by their interim performance. But the good-history managers respond to their midyear position and more so during the bull years. The evidence on risk-shifting is consistent with the evidence on how each incentive behaves for good and poor history managers over bull and bear phases. The fourth chapter shows that capital movement in and out of a mutual fund is more sensitive to fund performance during periods of high market volatility. I explain this result using a model where the manager has picking as well as timing skill. A volatile market presents an opportunity to generate timing value and to that extent produces speedy learning about managerial timing ability. Persistence in volatility boosts the sensitivity of flows to performance during such times. Given the counter-cyclical nature of market volatility, the model predicts that the flow sensitivity is higher during the recessions. Data supports the model prediction. The chapter provides a clear example when the trade volume (here capital flows) is linked positively with the volatility. Usually, literature has shown how the volatile periods slows the learning and hence trade volumes too. But my model indicates that there could be substantial learning going on during volatile times about critical economics parameters, mainly because those parameters are revealed only during volatile times.

A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada. / The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

O dimensionamento da tecnologia trouxe consequências indesejáveis para manter a taxa de crescimento exponencial e levanta questões importantes relacionadas com a confiabilidade e robustez dos sistemas eletrônicos. Atualmente, microprocessadores modernos de superpipeline normalmente contêm milhões de dispositivos com cargas nos nós cada vez menores. Esse fator faz com que os circuitos sejam mais sensíveis a variabilidade ambiental e aumenta a probabilidade de um erro transiente acontecer. Erros transientes em circuitos sequenciais ocorrem quando uma única partícula energizada deposita carga suficiente perto de uma região sensível. Flip-Flops mestreescravo são os circuitos sequencias mais utilizados em projeto VLSI para armazenamento de dados. Se um bit-flip ocorrer dentro deles, eles perdem a informação prévia armazenada e podem causar um funcionamento incorreto do sistema. A fim de proporcionar sistemas mais confiáveis que possam lidar com os efeitos da radiação, este trabalho analisa o Fator de Vulnerabilidade Temporal (Timing Vulnerability Factor - TVF) em algumas topologias de flip-flops mestre-escravo em estágios de pipeline sob diferentes condições de operação. A janela de tempo efetivo que o bit-flip ainda pode ser capturado pelo próximo estágio é definido com janela de vulnerabilidade (WOV). O TVF corresponde ao tempo que o flip-flop é vulnerável a erros transientes induzidos pela radiação de acordo com a WOV e a frequência de operação. A primeira etapa deste trabalho determina a dependência entre o TVF com a propagação de falhas até o próximo estágio através de uma lógica combinacional com diferentes atrasos de propagação e com diferentes modelos de tecnologia, incluindo também as versões de alto desempenho e baixo consumo. Todas as simulações foram feitas sob as condições normais pré-definidas nos arquivos de tecnologia. Como a variabilidade se manifesta com o aumento ou diminuição das especificações iniciais, onde o principal problema é a incerteza sobre o valor armazenado em circuitos sequenciais, a segunda etapa deste trabalho consiste em avaliar o impacto que os efeitos da variabilidade ambiental causam no TVF. Algumas simulações foram refeitas considerando variações na tensão de alimentação e na temperatura em diferentes topologias e configurações de flip-flops mestre-escravo. Para encontrar os melhores resultados, é necessário tentar diminuir os valores de TVF, pois isso significa que eles serão menos vulneráveis a bit-flips. Atrasos de propagação entre dois circuitos sequenciais e frequências de operação mais altas ajudam a reduzir o TVF. Além disso, estas informações podem ser facilmente integradas em ferramentas de EDA para ajudar a identificar os flip-flops mestre-escravo mais vulneráveis antes de mitigar ou substituí-los por aqueles tolerantes a radiação. / Technology scaling has brought undesirable issues to maintain the exponential growth rate and it raises important topics related to reliability and robustness of electronic systems. Currently, modern super pipelined microprocessors typically contain many millions of devices with ever decreasing load capacitances. This factor makes circuits more sensitive to environmental variations and it is increased the probability to induce a soft error. Soft errors in sequential circuits occur when a single energetic particle deposits enough charge near a sensitive node. Master-slave flip-flops are the most adopted sequential elements to work as registers in pipeline and finite state machines. If a bit-flip happens inside them, they lose the previous stored information and may cause an incorrect system operation. To provide reliable systems that can cope with radiation effects, this work analysis the Timing Vulnerability Factor (TVF) of some master-slave D flip-flops topologies in pipeline stages under different operating conditions. The effective time window, which the bit-flip can still be captured by the next stage, is defined as Window of Vulnerability (WOV). TVF corresponds to the time that a flip-flop is vulnerable to radiation-induced soft errors according to WOV and clock frequency. In the first step of this work, it is determined the dependence between the TVF with the fault propagation to the next stage through a combinational logic with different propagation delays and with different nanometer technological models, including also high performance and low power versions. All these simulations were made under the pre-defined nominal conditions in technology files. The variability manifests with an increase or decreases to initial specification, where the main problem is the uncertainty about the value stored in sequential. In this way, the second step of this work evaluates the impact that environmental variability effect causes in TVF. Some simulations were redone considering supply voltage and temperature variations in different master-slave D flip-flop topologies configurations. To achieve better results, it is necessary to try to decrease the TVF values to reduce the vulnerability to bit-flips. The propagation delay between two sequential elements and higher clock frequencies collaborates to reduce TVF values. Moreover, all the information can be easily integrated into Electronic Design Automation (EDA) tools to help identifying the most vulnerable master-slave flip-flops before mitigating or replacing them by radiation hardened ones.

Este trabalho introduz o conceito de cortes k e cortes kl sobre um circuito mapeado, em uma representação netlist. Esta nova abordagem é derivada do conceito de cortes k e cortes kl sobre AIGs (and inverter graphs), respeitando as diferenças entre essas duas formas de representar um circuito. As principais diferenças são: (1) o número de entradas em um nodo do grafo, e (2) a presença de inversores e buffers de forma explícita no circuito mapeado. Um algoritmo para enumerar cortes k e cortes kl é proposto e implementado. A principal motivação de usar cortes kl sobre circuitos mapeados é para realizar otimizações locais na síntese lógica de circuitos digitais. A principal contribuição deste trabalho é uma abordagem nova de remapeamento iterativo, utilizando cortes kl, reduzindo a área do circuito e respeitando as restrições de temporização do circuito. O uso de portas lógicas complexas pode potencialmente reduzir a área total de um circuito, mas elas precisam ser escolhidas corretamente de forma a manter as restrições de temporização do circuito. Ferramentas comerciais de síntese lógica trabalham melhor com portas lógicas simples e não são capazes de explorar eventuais vantagens em utilizar portas lógicas complexas. A abordagem proposta de remapeamento iterativo utilizando cortes kl é capaz de explorar uma quantidade maior de portas lógicas com funções lógicas diferentes, reduzindo a área do circuito, e mantendo as restrições de temporização intactas ao fazer uma checagem STA (análise temporal estática). Resultados experimentais mostram uma redução de até 38% de área na parte combinacional de circuitos para um subconjunto de benchmarks IWLS 2005, quando comparados aos resultados de ferramentas comerciais de síntese lógica. Outra contribuição deste trabalho é um novo modelo de rendimento (yield) para fabricação de circuitos integrados (IC) digitais, considerando problemas de resolução da etapa de litografia como uma fonte de diminuição do yield. O uso de leiautes regulares pode melhorar bastante a resolução da etapa de litografia, mas existe um aumento de área significativo ao se introduzir a regularidade. Esta é a primeira abordagem que considera o compromisso (trade off) de portas lógicas com diferentes níveis de regularidade e diferentes áreas durante a síntese lógica, de forma a melhorar o yield do projeto. A ferramenta desenvolvida de remapeamento tecnológico utilizando cortes kl foi modificada de forma a utilizar esse modelo de yield como função custo, de forma a aumentar o número de boas amostras (dies) por lâmina de silício (wafer), com resultados promissores. / This work introduces the concept of k-cuts and kl-cuts on top of a mapped circuit in a netlist representation. Such new approach is derived from the concept of k-cuts and klcuts on top of AIGs (and inverter graphs), respecting the differences between these two circuit representations. The main differences are: (1) the number of allowed inputs for a logic node, and (2) the presence of explicit inverters and buffers in the netlist. Algorithms for enumerating k-cuts and kl-cuts on top of a mapped circuit are proposed and implemented. The main motivation to use kl-cuts on top mapped circuits is to perform local optimization in digital circuit logic synthesis. The main contribution of this work is a novel iterative remapping approach using klcuts, reducing area while keeping the timing constraints attained. The use of complex gates can potentially reduce the circuit area, but they have to be chosen wisely to preserve timing constraints. Logic synthesis commercial design tools work better with simple cells and are not capable of taking full advantage of complex cells. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing circuit area, and respecting global timing constraints by performing an STA (static timing analysis) check. Experimental results show that this approach is able to reduce up to 38% in area of the combinational portion of circuits for a subset of IWLS 2005 benchmarks, when compared to results obtained from logic synthesis commercial tools. Another contribution of this work is a novel yield model for digital integrated circuits (IC) manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the lithography, but it results in a significant area overhead by introducing regularity. This is the first approach that considers the tradeoff of cells with different level of regularity and different area overhead during the logic synthesis, in order to improve overall design yield. The technology remapping tool based on kl-cuts developed was modified in order to use such yield model as cost function, improving the number of good dies per wafer, with promising interesting results.

Title: Electromyographic analysis of mutual relation between standing and movement pattern in shoulder girdle Objectives: This thesis examines the electric activity and recruitment (timing) of m. latissimus dorsi, m. obliquus externus abdominis, m. gluteus maximus, m. tensor fasciae latae, m. tibialis anterior, m. erector spinae and m. trapezius during shoulder girdle movement standing on both feet, ipsilateral or contralateral foot. Furthermore the thesis explores whether it is possible to objectify the existence of published tendomuscular chains or the whole hypothetic Latissimus dorsi muscle chain of Spiral stabilization concept using surface electromyography. Methods: The muscles mentioned above were measured bilaterally with surface electromyography electrodes during particular movements. Twelve healthy individuals participated, seven women and five men in the age of 23 - 30. All participants were instructed to do the specific movement from Spiral Stabilization concept against the 2kg resistence of elastic rope when standing on both feet or in one leg stand on contralateral or ipsilateral leg. Results: We can identify muscles that are active in the particular movements almost within all participants, that are activated less often and those that are involved rarely. But we are not able to...

This thesis targets the problem of critical path identification in sub-micron devices. Delays are described using Probability density functions (Pdfs) in order to model the probabilistic nature of the problem. Thus, a deterministic critical path response is not possible. The probability that each path is critical is reported instead. Extensive literature review has being done and presented in detail. Heuristics for accurate critical path calculations are described and results are compared to those from Monte Carlo simulations.

Depuis la découverte du premier pulsar en 1967, nous connaissons désormais plus de 2500 pulsars aujourd’hui. Les pulsars offrent un champ d’études considérable : depuis l’étude des propriétés du milieu interstellaire et l’étude de la magnétosphère des pulsars jusqu’aux tests de la gravité en champ fort et la caractérisation d’un fond d’ondes gravitationnelles d’origine cosmologique. Cela explique pourquoi nous continuons de chercher de nouveaux pulsars de nos jours. Après des découvertes de pulsars millisecondes dans les sources non identifiées du Fermi Large Area Telescope, un programme de recherche de nouveaux pulsars a été mené à partir de 2012 par G. Desvignes. Observant à 1.4 GHz avec une haute résolution temporelle et fréquentielle, le programme SPAN512 a été conçu pour la recherche de pulsars rapides et lointains situés dans le plan Galactique. Nous décrirons les méthodes d’analyse mises en place pour traiter les données afin de trouver de nouveaux pulsars, méthodes soit basées sur la stabilité de la période de rotation des pulsars soit sur leur émission d’impulsions individuelles. Nous présenterons aussi l’état actuel de l’analyse du programme SPAN512 et les découvertes effectuées, plus particulièrement du pulsar trouvé au cours de ce travail de thèse, PSR J2055+3829, un pulsar milliseconde de période de rotation de 2.08 ms appartenant à un système de type « Veuve Noire ». Ce sera l’occasion de présenter les études chronométriques réalisées pour trouver l’éphéméride de ce pulsar et, dans le même temps, j’en profiterai pour parler d’une analyse similaire faite sur le pulsar J1618-3921, un pulsar dans une orbite excentrique. Enfin, nous présenterons des études polarimétriques de pulsars réalisées à la lumière d’un nouveau modèle, le modèle du vecteur tournant décentré (DRVM). Nous montrerons qu’un champ magnétique hautement décentré peut expliquer les variations brusques de l’angle de polarisation. / Since the discovery of the first pulsar in 1967, we know over 2500 pulsars today. Pulsars offer a broad range of studies: from the study of the properties of interstellar medium and of pulsar magnetospheres up to test of gravity in the strong-field regime and the characterisation of the cosmological Gravitation Waves background. This explains why we keep searching pulsars nowadays. After successful detections of new millisecond pulsars in Fermi Large Area Telescope unassociated sources at Nançay, a blind pulsar survey was initiated in 2012 by G. Desvignes. Conducted at 1.4 GHz with short sampling time and narrow frequency channels, the SPAN512 was designed to find fast and distant pulsars within the Galactic plane. We describe the methods to analyse data in order to find new pulsars, thanks to their spin stability or tto their single pulses. We will also describe the current status of the survey and the discoveries, more especially the pulsar discovered during this thesis, PSR J2055+3829, a 2.08 ms pulsar in a black widow system. It will be the opportunity to present the radio timing analysis of this pulsar and, in the same time, we will describe similar studies conducted on the pulsar J1618-3921, a pulsar in an eccentric orbit. Finally, we present some polarisation studies of pulsars in light of a new model, the Decentred Rotating Vector Model (DRVM). We will show that a highly decentred dipole may explain abrupt variations of polarisation profiles.

L'existence des ondes gravitationnelles, fluctuations de l'espace-temps lui-même, a été prédite sans, pour l'instant, qu'une détection directe n'ait été encore possible. A l'heure actuelle, des méthodes consistant en des détecteurs interférométriques de plusieurs kilomètres de long sont à l'oeuvre pour permettre une première détection. Nous proposons, dans cette thèse, d'étudier une autre méthode : la chronométrie d'un réseau de pulsars milliseconde. Elle consiste en l'observation régulière et la datation précise des impulsions radio en provenance de pulsars ultrastables. L'onde gravitationnelle produisant retards ou avances des impulsions sur Terre, nous recherchons sa présence sous forme d'un signal corrélé entre les observations faites des différents pulsars du réseau. Dans un premier temps, nous détaillons les processus d'observation et de chronométrie des pulsars, pour nous pencher sur un cas particulier avec le pulsar J1614-2230. Puis, nous présentons les ondes gravitationnelles et leurs sources ainsi que les différentes méthodes de détection. Nous décrivons tout particulièrement la méthode de chronométrie d'un réseau de pulsars appliquée à la recherche d'un signal en provenance d'un système binaire de tous noirs supermassifs. Ensuite, après avoir détaillé les outils statistiques et numériques utilisés, nous appliquons notre méthode à l'injection d'un tel signal dans les observations réelles faites dans le cadre de l'EPTA. Enfin, nous présentons les limites supérieures sur l'amplitude d'un signal en provenance d'un système binaire obtenues sur ces données sans injection grâce à notre méthode en fonction de la fréquence et de la position de la source. / The existence of gravitational waves, ripples in space-time itself, has been predicted but their detection remains elusive. Multiple techniques exist for searching for them, including ground-based kilometer long inteferometers. In this thesis, we present an alternative approach, based on the monitoring and precise timing of radio pulses from an array of millisecond pulsars. A gravitational wave will perturb the propagation of those radio pulses, causing them to reach the Earth with a certain delay. By searching for correlations in the arrival times of the pulsations from different pulsars, we can in principle infer the presence of gravitational waves from observations. We begin by giving an overview of pulsar observations and timing. We illustrate those principles with a practical example : the study of the millisecond pulsar J1614-2230. In the second part we describe gravitational waves, the sources that create them, and the various detection methods. Then, we focus on the pulsar timing array technique, and its potential application to the search for gravitational waves from supermassive black hole binary system. We pursue with a detailed description of the statistical and numerical tools that we used in the present work, and present the results of a search ofr an injected signal in the real EPTA data set. Finally, we employ our new method to derive upper limits on the amplitude of a putative signal in the same EPTA data set, as a function of the frequency and sky location of the supermassive black hole binary system.

O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese física, o posicionamento visa espalhar as células na área disponível enquanto otimiza uma função custo obedecendo aos requisitos do projeto. Portanto, o posicionamento é uma etapa chave na determinação do comprimento total dos fios e, consequentemente, na obtenção da frequência de operação desejada. Técnicas de posicionamento incremental visam melhorar a qualidade de uma dada solução. Neste trabalho, são propostas duas abordagens para o posicionamento incremental guiado à tempos de propagação através de suavização de caminhos e balanceamento de redes. Ao contrário dos trabalhos existentes na literatura, a formulação proposta inclui um modelo de atraso na função quadrática. Além disso, o posicionamento quadrático é aplicado incrementalmente através de uma operação, chamada de neutralização, que ajuda a manter as qualidades da solução inicial. Em ambas as técnicas, o comprimento quadrático de fios é ponderado pelo drive strength das células e a criticalidade dos pinos. Os resultados obtidos superam o estado-da-arte em média 9,4% e 7,6% com relação ao WNS e TNS, respectivamente. / The interconnection delay is a dominant factor for achieving timing closure in nanoCMOS circuits. During physical synthesis, placement aims to spread cells in the available area while optimizing an objective function w.r.t. the design constraints. Therefore, it is a key step to determine the total wirelength and hence to achieve timing closure. Incremental placement techniques aim to improve the quality of a given solution. Two quadratic approaches for incremental timing driven placement to mitigate late violations through path smoothing and net load balancing are proposed in this work. Unlike previous works, the proposed formulations include a delay model into the quadratic function. Quadratic placement is applied incrementally through an operation called neutralization which helps to keep the qualities of the initial placement solution. In both techniques, the quadratic wirelength is pondered by cell’s drive strengths and pin criticalities. The final results outperform the state-of-art by 9.4% and 7.6% on average for WNS and TNS, respectively.