Les expériences de physique des particules associées au collisionneur LHC devront traiter une collision toutes les 25 ns sur plusieurs centaines de milliers de voies de mesure. La quantité de données produites est considérable.<br> Sur l'expérience LHCb une unité de décision en effectue une première sélection. Nous proposons une solution pour sa réalisation. Il s'agit d'une électronique numérique pipelines à 40 MHz et réalisée en composants programmables avec des interfaces LVDS. Une première version du banc de test est présentée afin de générer des stimuli à la cadence de 40 MHz pour des mots jusqu'à 512 bits.<br> Le preshower fait partie du système calorimétrique de LHCb. Il est composé de 6000 voies de mesure. Le signal physique est d'abord mis en forme grâce à des intégrations analogiques sur 25ns sans temps mort (ASIC). Au bout de 20m de câble, les valeurs d'intégrales (en tension) sont numérisées puis traitées sur une centaine de cartes frontales.<br> La réalisation de prototypes de la partie de traitement des données ont permis de mettre en concurrence une technologie programmable et une technologie ASIC (AMS 0,35 µm) et de prendre en compte les contraintes fortes en terme de nombre de voies de mesure par carte (128 demi-voies) et de résistance aux radiations.

La maladie de Parkinson est la seconde maladie neuro-dégénérative la plus fréquente à travers le monde. Dans ce contexte, le projet de recherche associé à cette thèse vise à améliorer le traitement symptomatique de la maladie de Parkinson, par le développement de procédés de stimulation cérébrale profonde adaptative. Le travail de cette thèse repose sur la conception d'un ASIC d'enregistrement et de traitement de signaux neuronaux, répondant à divers enjeux :un traitement continu et en temps réel focalisé sur des bandes spécifiques très basses-fréquences et largement configurables. L'objectif est d'utiliser l'information traitée pour le contrôle et la génération d'un signal de stimulation. Cet ASIC a été développé, caractérisé électroniquement et utilisé dans un contexte in vivo. Un système en boucle fermée a été réalisé à partir de cet ASIC, se montrant fonctionnel. Ces validations expérimentales in vivo ouvrent de nombreuses possibilités d'investigation du concept de stimulation cérébrale en boucle fermée.

<p>An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design. </p><p>Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippetsinto actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated. </p><p>Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible. </p><p>The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.</p>

<p>Detta examensarbete gick ut på att försöka hitta ett sätt att mäta kompo nentkänslighet hos parameteriserbara aktiva vågfilter. Två olika ansatser har gjorts, men bara ett försök har avslutats. </p><p>Det första försöket behandlar möjligheten att realisera ett vågfilter med hjälp av standardkomponenter i en kretskortslösning. Detta fungerade inte beroende på att nödvändiga komponenter inte finns på marknaden idag. Komponenterna som finns har för stora parasitkapacitanser. Dessa oönskade parasiter var så stora att de skulle kunna förstöra funktionen och det var således inte värt att fortsätta försöket. De komponenter som undersöktes var resistansstegar och digitala potentiometrar. Den största delen av studierna till det första försöket har bestått i att studera datablad från olika kretstillverkare för att hitta lämpliga komponenter. </p><p>Istället startades ett nytt försök som syftade till att undersöka möjligheten att implementera ett aktivt vågfilter i en integrerad krets. I denna rapport presenteras en förstudie till hur en sådan lösning skulle kunna se ut. För att möjliggöra en fortsättning där mitt examensarbete tar slut har arbetet förklarats ingående. Jag har också inkluderat min programkod som bilagor i slutet av rapporten.</p> / <p>The purpose of this thesis was to find a way of measuring the sensitivity of component values for parameterized wave active filters. Two different approaches were made, but only one was finished. </p><p>The first approach is about the possibility of making a wave active filter with standard components on a printed circuit board. This did not work though, because of a scarce market of possible components. The compo-nents existing today have too high parasite capacitances. These unwanted parasites are so large in value that they could destroy the functionality and it was therefore not worth continuing the attempt. The components that were investigated as possible on the board were ladder networks and digitally controlled potentiometers. The main part of the studies for the first attempt was to read data sheets from different electronic companies trying to find possible components. </p><p>Instead a new approach was made with the purpose of investigating the possibility of making a wave active filter as an integrated circuit. In this report a pilot study for such an attempt is presented. To make it possible to continue work where these studies end, the work has been carefully explained. I have also included the computer programs I have made in the appendix of the report.</p>

<p>The goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.</p>

<p>With increasing demands in terms of timing, area and power, today’s ASIC (Application Specific Integrated Circuit) designers are faced with new problems as technology emerges. Ericsson has started to work in 65 nm and realized that the methods used in previous, larger technologies, does not offer good enough correlation between synthesis and the results after physical placement. This leads to several expensive and time consuming iterations back and forth between Ericsson and the ASIC vendor.</p><p>In order to narrow the gap between Ericsson and the ASIC vendor, and hence increase correlation, physical planning has been identified as a possible solution. Cadence First Encounter, part of the Cadence Encounter digital IC design platform, is an advanced tool for silicon virtual prototyping. The tool basically brings back-end placement knowledge to front-end ASIC designers.</p><p>This master’s thesis main goal is to evaluate Cadence First Encounter and investigate how it could be integrated with Ericsson’s design flow. The tool has been tested on previous designs with known issues and the results are positive. By using the prototype work flow in First Encounter that is described in this report, it is possible to identify and correct issues with the netlists in time, which will help shortening the lead time in projects and hence also the time to market.</p>

Digital computers have changed human society in a profound way over the last 50 years. Key properties that contribute to the success of the computer are flexible programmability and fast access to large amounts of data and instructions. Effective access to algorithms and data is a fundamental property that limits the capabilities of computer systems. For PC computers, the main memory consists of dynamic random access memory (DRAM). Communication between memory and processor has traditionally been performed over a multi-drop bus. Signal frequencies on these buses have gradually increased in order to keep up with the progress in integrated circuit data processing capabilities. Increased signal frequencies have exposed the inherent signal degradation effects of a multidrop bus structure. As of today, the main approach to tackle these effects has been to reduce the number of endpoints of the bus structure. Though improvements in DRAM memory technology have increased the available memory size at each endpoint, the increase has not been able to fully fulfill the demand for larger system memory capacity. Different bus structural changes have been used to overcome this problem. All are different compromises between access latency, data transmission capacity, memory capacity, and implementation costs. In this thesis we focus on using the signal processing capabilities of a modern integrated circuit technology as an alternative to bus structural changes. This has the potential to give low latency, high memory capacity, and relatively high data transmission capacity at an additional cost limited to integrated circuit blocks. We first use information theory to estimate the unexplored potential of existing multi-drop bus structures. Hereby showing that reduction of the number of endpoints for multi-drop buses, is by no means based on the fundamental limit of the data transmission capacity of the bus structure. Two test-chips have been designed and fabricated to experimentally demonstrate the feasibility of several Gb/s data-rates over multidrop buses, with limited cost overhead and no latency penalty. The test-chips implement decision feedback equalization, adopted for high speed multi-drop use. The equalizers feature digital filter implementations which, in combination with high speed DACs, enable the use of long digital filters for high speed decision feedback equalization. Blind adaptation has also been implemented to demonstrate extraction of channel characteristics during data transmission. The use of single sided equalization has been proposed in order to limit the need for equalization implementation to the host side of a DRAM memory bus. Furthermore, we propose to utilize the reciprocal properties of the communication channel to ensure that single sided equalization can be performed without any channel characterization hardware on the memory chips. Finally, issues related to evaluation of high-speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.

The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4x4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.

Trellis-coded Modulation (TCM) is used in bandlimited communication systems. TCM efficiency improves coding gain by combining modulation and forward error correction coding in one process. In TCM, the bandwidth expansion is not required because it uses the same symbol rate and power spectrum; the differences are the introduction of a redundancy bit and the use of a constellation with double points. <p> In this thesis, a novel TCM encoder/decoder ASIC chip implementation is presented. This ASIC codec not only increases decoding speed but also reduces hardware complexity. The algorithm and technique are presented for a 16-state convolutional code which is used in standard 256-QAM wireless systems. In the decoder, a Hamming distance is used as a cost function to determine output in the maximum likelihood Viterbi decoder. Using the relationship between the delay states and the path state in the Trellis tree of the code, a pre-calculated Hamming distances are stored in a look-up table. In addition, an output look-up-table is generated to determine the decoder output. This table is established by the two relative delay states in the code. The thesis provides details of the algorithm and the structure of TCM codec chip. Besides using parallel processing, the ASIC implementation also uses pipelining to further increase decoding speed. <p> The codec was implemented in ASIC using standard 0.18Ým CMOS technology; the ASIC core occupied a silicon area of 1.1mm2. All register transfer level code of the codec was simulated and synthesized. The chip layout was generated and the final chip was fabricated by Taiwan Semiconductor Manufacturing Company through the Canadian Microelectronics Corporation. The functional testing of the fabricated codec was performed partially successful; the timing testing has not been fully accomplished because the chip was not always stable.

Trellis-coded Modulation (TCM) is used in bandlimited communication systems. TCM efficiency improves coding gain by combining modulation and forward error correction coding in one process. In TCM, the bandwidth expansion is not required because it uses the same symbol rate and power spectrum; the differences are the introduction of a redundancy bit and the use of a constellation with double points. <p> In this thesis, a novel TCM encoder/decoder ASIC chip implementation is presented. This ASIC codec not only increases decoding speed but also reduces hardware complexity. The algorithm and technique are presented for a 16-state convolutional code which is used in standard 256-QAM wireless systems. In the decoder, a Hamming distance is used as a cost function to determine output in the maximum likelihood Viterbi decoder. Using the relationship between the delay states and the path state in the Trellis tree of the code, a pre-calculated Hamming distances are stored in a look-up table. In addition, an output look-up-table is generated to determine the decoder output. This table is established by the two relative delay states in the code. The thesis provides details of the algorithm and the structure of TCM codec chip. Besides using parallel processing, the ASIC implementation also uses pipelining to further increase decoding speed. <p> The codec was implemented in ASIC using standard 0.18Ým CMOS technology; the ASIC core occupied a silicon area of 1.1mm2. All register transfer level code of the codec was simulated and synthesized. The chip layout was generated and the final chip was fabricated by Taiwan Semiconductor Manufacturing Company through the Canadian Microelectronics Corporation. The functional testing of the fabricated codec was performed partially successful; the timing testing has not been fully accomplished because the chip was not always stable.