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El presente trabajo de investigación aborda la problemática del daño por radiación en disposi- tivos, ciruitos y sistemas microelectrónicos, situación que se presenta habitualmente cuando los mismos son utilizados en aplicaciones espaciales o nucleares. Durante el desarrollo de la tesis se propone una metodología integrada por diferentes técnicas de diseño que permiten incrementar la tolerancia a este tipo de fallas en los sistemas. Asimismo, se detallan los ensayos de radiación realizados para validar la metodología y las contribuciones aportadas en dichos procedimientos. El material presentado se articula en dos partes, dividiéndose el mismo en función del tipo de fenómeno con el que se pueden asociar los distintos tipos de fallas inducidas por radiación. En la primera parte se presenta el problema de daño acumulativo, mientras que en la segunda se trata el problema de errores producidos por fallas transitorias. En ambas partes se introduce primero la problemática, para luego pasar a detallar lo realizado paracombatir sus efectos y finalmente describir los procedimientos de validación experimental. Temas como tecnología CMOS, entorno de radiación espacial y metodología de seleción de partes para misiones espaciales han sido incor- porados en apéndices, a modo de referencia. La validez de la metodología propuesta se encuentra respaldada con la fabricaión de más de seis ciruitos integrados, donde las implementaciones físicas de los diseños fueron realizadas en diversas tecnologías modernas utilizando las técnicas propuestas. Los resultados experimentales fueron obtenidos durante la realización de diversos ensayos de irradiación en aceleradores de partículas con iones pesados y protones de alta energía. / This research deals with the issues that arise due to radiation damage in microelectronic devices, circuits and systems, a situation that occurs often in nuclear and space applications. Throughout this thesis, a method will be presented that is composed of different design techni- ques that aim to increase the system's tolerance to this type of damage. Furthermore, radiation experiments are presented which serve both to validate this methodology and also provide valua- ble contributions on the subject. The text is presented in two parts, each studying one phenomena that can be associated with acertain type of system failure induced by radiation. The first part introduces the effects ofcumulative damage while the second part deals with errors that occur due to sudden failures or conditions. Each part is structured as follows: the main problem is introduced, the possible solutions are presented and finally the experiments that validate the methods are explained. Complementary data which includes CMOS technology, space radiation environment and part selection methodology for space missions is included in the form of ap- pendixes, to provide background information. The main body of work is validated by the design and fabrication of over six different integrated circuits in several modern technologies using the proposed techniques. The results of several radiation tests were obtained in particle accelerators through the use of heavy ions and high-energy protons.

A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum. In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,…,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time. To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech. Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one. / Ph. D.

Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can possibly be disastrous due to repeated use of the cell in a design. In this thesis, we investigated ways to automate the process for development of a cell library, specifically TSMC 0.18-micron CMOS standard cell library. We examined various steps in the design flow to identify required repetitive tasks for individual cells. Those steps include physical verification, netlist extraction, cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of verifying the entire ASIC design flow adopted for the Virginia Tech VLSI Telecommunications (VTVT) lab. Our scripts have been successfully used to develop our TSMC 0.18-micron library and to verify the quality assurance. The first version of the cell library was released on November 1, 2007 to universities worldwide, and as of March 2008, 20 universities have received the library from us. / Master of Science