Le travail présenté dans ce manuscrit a été effectué au sein de l'équipe de microélectronique de l'Institut de Recherche sur les lois Fondamentales de l'Univers (IRFU) du CEA. Il s'inscrit dans le contexte de la spectro-imagerie X et gamma pour la recherche en Astrophysique. Dans ce domaine, les futures expériences embarquées à bords de satellites nécessiteront des instruments d'imagerie à très hautes résolutions spatiales et énergétiques.La résolution spectrale d'une gamma-camera est dégradée par l'imperfection du détecteur lors de l'interaction photon-matière lui-même et par le bruit électronique. Si on ne peut réduire l'imprécision de conversion photon-charge du détecteur, on peut minimiser le bruit apporté par l'électronique de lecture. L'objectif de cette thèse est la conception d'une électronique intégrée de lecture de détecteur semi-conducteurs CdTe pixélisés pour gamma-caméra(s) compacte(s) et aboutable(s) sur 4 côtés à résolution spatiale " Fano limitée ". Les objectifs principaux de ce circuit intégré sont: un très bas bruit pour la mesure d'énergie des rayons-X, une très basse consommation, et une taille de canal de détection adaptée au pas des pixels CdTe. Pour concevoir une telle électronique, chaque paramètre contribuant au bruit doit être optimisé. L'hybridation entre l'électronique de lecture et le détecteur est également un paramètre clef qui fait généralement la résolution finale de l'instrument : en imposant une géométrie matricielle à l'ASIC adaptée au pas de 300 µm des pixels de CdTe, on peut espérer, réduire d'un facteur 10 la capacité parasite amenée par la connexion détecteur-électronique et améliorer d'autant le bruit électronique tout en conservant une densité de puissance constante. Une bonne connaissance des propriétés du détecteur nous permet alors d'extraire ses paramètres électroniques clefs pour concevoir l'architecture électronique de conversion et de filtrage optimale. Dans le cadre de cette thèse j'ai conçu deux circuits intégrés en technologies CMOS XFAB 0.18 µm. Le premier, Caterpylar, est destiné à caractériser cette nouvelle technologie, y compris en radiation, identifier un étage d'entrée pour le pixel adapté au détecteur, et valider par la mesure les résultats théoriques établis sur deux architectures de filtrage, semi gaussien et " Multi-Correlated Double Sampling " (MCDS), approchant l'efficacité du filtrage optimal et adaptées aux applications finales. Le deuxième circuit, D2R1, est un système complet, constitué de 256 canaux de lecture de détecteur CdTe, organisés dans une matrice de 16×16 pixels. Chaque canal comprend un préamplificateur de charge adapté à des pixels de 300 μm×300 μm, un opérateur de filtrage de type MCDS de profondeur programmable, d'un discriminateur auto-déclenché à bas seuil de détection programmable par canal. L'ASIC a été caractérisé sans détecteur et est en voie d'être hybridé à une matrice de CdTe très prochainement. Les résultats de caractérisations de la puce nue, en particulier en terme de produit puissance × bruit, sont excellents. La consommation de la puce est de 315 µW/ canal, la charge équivalente de bruit mesurée sur tous les canaux est de 29 électrons rms. Ces résultats valident le choix d'intégration d'un filtrage de type MCDS, qui est, à notre connaissance une première mondiale pour la lecture de détecteurs CdTe. Par ailleurs, ils nous permettent d'envisager d'excellentes résolutions spectrales de l'ensemble détecteur+ASIC, de l'ordre de 600 eV FWHM à 60 keV.

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The battery driven nature of wireless sensor networks, combined with the need of extended lifetime mandates that energy efficiency is a metric with high priority. In the current thesis we explore and compare the energy dissipation of di fferent processor architectures and how it is associated with performance and area requirements. The processor architectures are di erentiated based on the datapath length (16-bit, 32-bit, 64-bit and 128-bit) and the corresponding size of the data memories. Our study focuses on AES algorithm, and the indicated processor architectures support AES forward encryption, CCM (32/64/128), CBC (32/64/128) and CTR common modes of operation. In each processor architecture the instruction set is extended to increase the efficiency of the system. / -

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

abstract: Static CMOS logic has remained the dominant design style of digital systems for more than four decades due to its robustness and near zero standby current. Static CMOS logic circuits consist of a network of combinational logic cells and clocked sequential elements, such as latches and flip-flops that are used for sequencing computations over time. The majority of the digital design techniques to reduce power, area, and leakage over the past four decades have focused almost entirely on optimizing the combinational logic. This work explores alternate architectures for the flip-flops for improving the overall circuit performance, power and area. It consists of three main sections. First, is the design of a multi-input configurable flip-flop structure with embedded logic. A conventional D-type flip-flop may be viewed as realizing an identity function, in which the output is simply the value of the input sampled at the clock edge. In contrast, the proposed multi-input flip-flop, named PNAND, can be configured to realize one of a family of Boolean functions called threshold functions. In essence, the PNAND is a circuit implementation of the well-known binary perceptron. Unlike other reconfigurable circuits, a PNAND can be configured by simply changing the assignment of signals to its inputs. Using a standard cell library of such gates, a technology mapping algorithm can be applied to transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. This approach was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier in 65nm LP technology. Simulation and chip measurements show more than 30% improvement in dynamic power and more than 20% reduction in core area. The functional yield of the PNAND reduces with geometry and voltage scaling. The second part of this research investigates the use of two mechanisms to improve the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM devices for low voltage operation. The third part of this research focused on the design of flip-flops with non-volatile storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated with both conventional D-flipflop and the PNAND circuits to implement non-volatile logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of system locally when a power interruption occurs. However, manufacturing variations in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading to an overly pessimistic design and consequently, higher energy consumption. A detailed analysis of the design trade-offs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5X more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are designed with the same backup and restore circuitry in 65nm technology. The embedded logic in NV-TLFF compensates performance overhead of NVL. This leads to the possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and- accumulate (MAC) unit is designed to demonstrate the performance benefits of the proposed architecture. Based on the results of HSPICE simulations, the MAC circuit with the proposed NV-TLFF cells is shown to consume at least 20% less power and area as compared to the circuit designed with conventional DFFs, without sacrificing any performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células pré-customizadas para gerar sistemas digitais mais complexos. Portanto a eficiência de um projeto ASIC está relacionado com a biblioteca em uso. A utilização de portas lógicas CMOS geradas automaticamente no fluxo de projeto de circuito integrado baseado em células-padrão representa uma perspectiva atraente para melhorar a qualidade de projeto ASIC. Essas células geradas por software são os elementos-chave dessa nova abordagem de mapeamento tecnológico livre de biblioteca, já proposto na literatura e agora adotado pela indústria. O mapeamento tecnológico livre de biblioteca, baseado na criação de células sob demanda, por software, gera flexibilidade aos projetistas de circuitos integrados, fornecendo ajuste otimizado em aplicações específicas. Contudo, tal abordagem representa um fluxo de projeto de circuito integrado baseado em células lógicas criadas sob demanda por software, as quais não são previamente validadas em silício até que o ASIC alvo seja prototipado. Neste trabalho, um circuito de teste específico é proposto para validar a funcionalidade completa de um conjunto de células lógicas, bem como verificar comportamentos de atraso e consumo, os quais podem ser correlacionados com as estimativas de atraso e consumo do projeto, a fim de validar os dados das células gerados pela caracterização elétrica. A arquitetura proposta para o circuito de teste é composta por blocos combinacionais que garantem a completa verificação lógica de cada célula da biblioteca. A estrutura básica do circuito de teste é ligeiramente modificada para permitir diferentes modos de operação que permitem avaliação de diferentes dados utilizando simulações elétricas SPICE. Visto que o circuito de teste gera pequeno acréscimo de silício ao projeto final, ele pode ser implementado junto com o ASIC alvo, atuando como um ‘circuito de certificação de biblioteca’. / Cell-based design is the most applied approach in the ASIC market today. This design approach implies re-using pre-customized cell libraries to build more complex digital systems. Therefore the ASIC design efficiency turns to be bounded by the library in use. The use of automatically generated CMOS logic gates in standard cell IC design flow represents an attractive perspective for ASIC design quality improvement. These soft IPs (logic cells generated by software) are the key elements for the novelty libraryfree technology mapping, already proposed in literature and now being adopted by the industry. Library-free technology mapping approach, based on the on-the-fly creation of cells, by software, can provide flexibility to IC designers providing an optimized fit in a particular application. However, such approach represents an IC design flow based on logic cells created on-the-fly by software which have not been previously validated in silicon yet, until the target ASIC is prototyped. In this work, a specific test circuit (testbench) is proposed to validate the full functionality of a set of logic cells, as well as to verify timing and power consumption behaviors, which can be correlated with design timing and power estimations in order to validate the cell data provided by electrical characterization. The proposed architecture for the test circuit is composed by combinational blocks that ensure full logic verification of every library cell. The basic architecture of the test circuit is slightly modified to allow different operating modes which provide distinct data evaluation using SPICE electrical simulations. Since this test circuit brings little silicon overhead to the final design, it can be implemented together with the target ASIC acting as a ‘library certification circuit’.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第17160号 / 工博第3650号 / 新制||工||1554(附属図書館) / 29899 / 京都大学大学院工学研究科電気工学専攻 / (主査）教授 山川 宏, 教授 北野 正雄, 教授 篠原 真毅 / 学位規則第4条第1項該当

By adapting Mitchell's algorithm for floating-point numbers, one can efficiently perform arithmetic floating-point operations in an approximate logarithmic domain in order to perform approximate computations of functions such as multiplication, division, square root and others. This work examines how this algorithm can be improved in terms of accuracy and hardware complexity by applying a set of various methods that are parametrized and offer a large design space. Optimal coefficients for a large portion of this space is determined and used to synthesize circuits for both ASIC and FPGA circuits using the bfloat16 format\@. Optimal configurations are then extracted to create an optimal curve where one can select an acceptable error range and obtain a circuit with a minimal hardware cost.

The thesis deals with design of novel circuit structure suitable for hardware implementations of feedforward neural networks. The structure utilizes innovative data bus structure. The main contribution of the structure is in optimization of the utilization of implemented computing units. Proposed architecture is flexible and suitable for implementations of variety of feedforward neural network structures.