One of the modern times worst environmental problem are polluted water resources. An example of source of pollution to water resources are, heavy metal leached from acid sulfate soils (ASS). When these soils are stable, which they are if they are left underwater in an anoxic environment (for example below the water table), they are often sought after since they consist of high amount of nutrients which farmers use as farmlands. ASS is therefore created when farmers drain their land and the sulfide soil gets exposed to air, resulting in its oxidation and therefore formation of sulfuric acid. In a previous study performed by scientists from Linnaeus University, it was concluded that a natural reserve located in Vattenriket, Kristianstad was possibly damaged by the drainage discharge of an adjacent acid sulfate soil. For remediation of acid sulfate soil, notably removal of metals from drainage waters, grounded coffee has been suggested to be able to perform well as an adsorbent. This study was performed to investigate how well grounded coffee could be used as an adsorbent, for calcium (Ca) and zinc (Zn), from water samples collected in Vattenriket, Kristianstad. It was also studied to see if grounded coffee could be cleaned using a sodium hydroxide solution to increase its adsorption capacity. To be able to evaluate how well it could be used as an adsorbent, it went through two different cleaning procedures and total organic carbon and pH readings was performed. The used method for this paper was to clean the grounded coffee in two different stages. The first stage consisted of using distilled water and letting it run through the residues until the water came out as transparent. Cleaning using a NaOH solution consisted of suspending the residues in a NaOH solution for 45 minutes and swapping the solution 6-8 times. After the grounded coffee had dried in an oven at 30o for 48 hours, it was put into different fraction sizes, weighed and bagged. The water samples then had to be filtered using a pump and Filtropur S 0.45 filters. Lastly, 45 falcon tubes containing 15 different amounts of grounded coffee had 50 ml of filtered water sample added to them. For analysis, atomic absorption spectroscopy was used. The results showed that the maximum amount of adsorbed calcium was achieved at 1.5g of grounded coffee in a 50 ml water solution which managed to adsorb 99.53% of calcium. The maximum amount of adsorbed zinc was achieved at 1.25g of grounded coffee in a 50 ml solution which resulted in 99.16% of adsorbed zinc. The study also showed that when the total organic carbon-content was decreasing, due to excessive cleaning, the pH was increasing. This was further proof that the grounded coffee still had residues onto its surface that could inhibit its adsorption capabilities.

Le roman Les Métamorphoses d'Apulée se distingue par les nombreux récits insérés qu’il contient et qui interrompent fréquemment la trame principale. Ces histoires étaient probablement déjà présentes en partie dans le roman grec qui a servi de source à Apulée, les Μεταμορφώσεις. Cependant, ce texte ne nous étant parvenu que sous une forme abrégée (l'ὄνος), il demeure difficile de déterminer à quel point la structure de la version latine des Métamorphoses retient de celle de l’original grec. Certes, certains éléments sont facilement attribuables à Apulée, comme le conte de Cupidon et Psyché, ou encore le 11ème et dernier livre du roman. En plus d’être divertissants, ces récits insérés reprennent les thèmes principaux exploités dans le roman, renforçant la cohérence de celui-ci. Par ailleurs, toutes ces histoires secondaires nécessitent l’intervention de plusieurs narrateurs et, en plus de Lucius (personnage et narrateur principal), divers personnages prennent la parole. Enfin, Apulée accorde aussi une grande attention à la perception que ses personnages ont des événements dont ils sont témoins ou des histoires qui leur sont rapportées. À plusieurs reprises, la subjectivité des personnages influence le récit. Ainsi, les histoires insérées des Métamorphoses, qui peuvent donner l’impression que la trame du récit est brouillonne, sont au contraire l’élément le plus original et le mieux développé du roman. / The Metamorphoses of Apuleius is notable for its numerous inserted tales often interrupting the novel’s main plot. These stories were probably already present, at least partly, in the Greek novel that was used as a source by Apuleius, the Μεταμορφώσεις. However this work is lost and only reached us through an epitomized version (Ὄνος), making it difficult to establish just how much the structure of the Latin Metamorphoses retains from its Greek source. Still some elements can be easily attributed to Apuleius, like Cupid and Psyche’s tale or the novel's 11th (and last) book. Besides having an entertaining purpose, these inserted tales share common themes with the main plot, creating a unity within the novel. Furthermore, multiple narrators are required in order to tell all these stories implying that, in addition to Lucius (the novel’s main character and narrator), many characters play an active part in storytelling. Finally, Apuleius pays great attention to his characters’ perception of events they witness or of stories they hear. And at several occasions the characters’ subjectivity influences the storyline. Thus the Metamorphoses’ inserted tales, even though they may at first give a false impression of confusion, should be considered as the most original and most well developed feature of Apuleius’ novel.

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-05-21T13:19:36Z No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-01T12:13:22Z (GMT) No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) / Made available in DSpace on 2018-06-01T12:33:57Z (GMT). No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) Previous issue date: 2018-03-28 / ? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia natural de um circuito implementado com Blade, onde o monitoramento cont?nuo para detec??o de viola??es de atraso fornece a informa??o necess?ria para a detec??o concorrente de viola??es que extrapolam a capacidade de recupera??o do circuito resiliente. A integra??o de todas as contribui??es fornece uma cobertura de falha satisfat?ria para um custo de ?rea que, para os circuitos avaliados nesta Tese, pode variar de 4,24% a 6,87%, enquanto que a abordagem Scan para os mesmos circuitos apresenta custo que varia de 50,19% a 112,70% em ?rea, respectivamente. As contribui??es desta Tese demonstraram que, com algumas melhorias na arquitetura do Blade, ? poss?vel expandir sua confiabilidade para al?m de um sistema de toler?ncia a viola??es de atraso no caminho de dados, e tamb?m um avan?o para teste de falhas (inclusive falhas online) de todo o circuito, bem como melhorar seu rendimento, e lidar com quest?es de envelhecimento. / As the VLSI design moves into ultra-deep-submicron technologies, timing margins added due to variabilities in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance and/or reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise after designing the circuit with reduced time margins. Asynchronous systems, on the other hand, have a potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. Asynchronous circuits can also present advantages for functional testing, and the timing resilient characteristic provides continuous feedback during normal circuit operation, which can be applied for concurrent testing. In this Thesis, Blade?s testability is evaluated from a different perspective, where circuits implemented with Blade present reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a Blade circuit, where the continuous monitoring for detecting timing violations provide the necessary feedback for online detection of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overhead that, for the evaluated circuits in this thesis, can vary from 4.24% to 6.87%, while the scan approach for the same circuits implies an area overhead varying from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also advances for fault testing (including online faults) of the entire circuit, yield, and aging.

Diploma thesis Bc. Anna Fauknerová (2018) Transformationand Adaptation of the Cupid and Psyche Myth in Literature Abstract This thesis deals with the myth of Cupid and Psyche. It is concerned with the version of the myth found in Apulei's novel The Golden Ass as well as in other works such as fairy tales and novels. Some of these other works refer to the myth directly while others' connections to it have not been established and they merely demonstrate similar motifs. The first part of the thesis deals with Apuleius and his text The Golden Ass, which is the oldest surviving version of the myth of Amor and Psyche. The main characteristics of the myth as well as its characters, the story and the meanings that are hidden in it are examined. The character of Psyche and the way her heroism manifests itself are examined in greater detail. The second part of the thesis compares the myth with three fairy tales and three novels based on the conclusions of the previous chapter. The greatest emphasis is placed on the development and adaptation of individual motifs, similarities and disimilarities in content and form and on the way in which the myth is reflected in literature. The third part of the thesis looks at three possible ways of interpreting the myth. Keywords: Cupid, Psyche, myth, fairy tale, motif of light...

In this study, I investigated the interactions between multiple intelligences and performance of learners in open-ended digital learning tasks, and to suggest possible approaches to the teaching and learning process using computers in Tanzania. With the current introduction of computers in the education system in Tanzania, the qualities of instruction and learner participation in learning computer application skills and achievement have not necessarily shown improvement (Nelson, Post,&Bickel, 2003; Tilya, 2003). It is imperative for computer teachers to know the pedagogical strategies that can help them use the current technology effectively. Researchers in instructional design have suggested instructional methods that incorporate methods that encourage the use of learner-centered instruction, incorporating activity oriented methods, and problem solving that are designed around real-world problems (Huba&Freed, 2000). Learners will be able use their knowledge effectively, reveal their uniqueness as learners, and learn computer application skills in a social setting (Gardner, 1983; Wiggins, 1993, 1998; Teele, 2000; Huba&Freed, 2000). The theory of multiple intelligences by Howard Gardner (1983) was used as the theoretical framework for this study. The theory postulates that that everybody has at least eight intelligences which reflect different ways of interacting with the world. In an effort to achieve quality learning, learning must be based on multiple approaches with a series of activities which are authentic in nature and have to be completed by the learners. The study was conducted in Tanzania using a qualitative research design. Four secondary schools were selected and 40 learners doing computer studies course participated in the study. Four intelligences from the theory of multiple intelligences were assessed: logic-mathematical, verbal-linguistic, visual-spatial and interpersonal intelligences. Assessment was done using performance assessment procedures. The findings indicated that there are distinctive intelligence profiles apart from the four intelligences that were investigated in this study. Despite the intelligence profiles of the learners, didactical issues that will enhance ICT adoption in the education environment are important. These include the use of authentic tasks, performance assessment to acknowledge learners unique performance abilities across several intelligences and teachers familiarization in the use of performance assessment procedures. / Thesis (PhD (Curriculum Studies))--University of Pretoria, 2008. / Curriculum Studies / unrestricted

Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-08-22T17:30:17Z No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-08-23T12:09:32Z (GMT) No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) / Made available in DSpace on 2018-08-23T13:31:43Z (GMT). No. of bitstreams: 1 GUILHERME HECK_TES.pdf: 7520580 bytes, checksum: 0abf48b5a455b7c50fa0b30109a1ee57 (MD5) Previous issue date: 2018-03-09 / A demanda sem precedentes por poderosos dispositivos de processamento gerou quebras consecutivas de paradigma de projeto de circuito na ?rea de Circuitos Integrados (CIs). O uso de tecnologia submicrom?trica profunda aumenta a densidade de integra??o a n?veis nunca vistos antes. No entanto, com CIs mais densos, a inclina??o do rel?gio e outros efeitos requerem compensa??es em design s?ncrono, o que pode aumentar a ?rea e o consumo de energia a valores inaceit?veis. Como alternativa, o paradigma ass?ncrono est? re-emergindo, focado na efici?ncia de energia. Entre os modelos cl?ssicos de projeto ass?ncrono, o Empacotamento-de-Dados (ED) se destaca pela sua capacidade de fornecer alto desempenho, reduzir a pot?ncia e obter resultados de ?rea semelhante ? dos modelos s?ncronos. Diferentemente dos modelos mais robustos de quase-atraso insens?vel, uma outra classe comum de modelos para implementar circuitos ass?ncronos, circuitos ED requerem o uso extensivo de Elementos de Atraso (EAs) para garantir a correta funcionalidade. No entanto, todos os circuitos s?o afetados por varia??es de Processo, Tens?o e Temperatura (PTT), incluindo a L?gica Combinacional (LC) em ED impondo margem em elementos de atraso. Al?m disso, projetos atuais usam escalonamento de tens?o para melhorar a efici?ncia de energia, o que afeta o atraso diferentemente em LCs e EAs adicionando mais margem em EAs. Um novo modelo baseado em ED chamado Blade usa o conceito de resili?ncia como uma esperan?a para evitar a margem de atraso causada por PTT e escalonamento de tens?o. Contudo, o uso de dois elementos de atraso ir? representar mais margens e mais tempo de teste no circuito final. Assim, este trabalho mostra uma an?lise do comportamento de elementos de atraso sob escalonamento de tens?o e o impacto em testes p?s-sil?cio. Ele introduz um novo termo para determinar o impacto da escala de tens?o sobre os elementos de atraso e tamb?m a compara??o entre os EAs mais utilizados em projetos ED usando esta nova m?trica. Uma an?lise de testes em modelos ED e Blade ? apresentada e o impacto da escala de tens?o nestes projetos ? analisado. Finalmente, um novo elemento de atraso ? proposto focando na redu??o de margem e redu??o no tempo de teste para o modelo Blade. / The unprecedented demand for powerful processing devices has generated consecutive circuit design paradigm breaks in the Integrated Circuits (ICs) arena. The use of deep submicron technology increases the integration density to levels never seen before. However, with denser ICs, clock skew and other effects require compensations in synchronous design, which can increase area overhead and power consumption to unacceptable values. As an alternative, the asynchronous paradigm is re-emerging, focused on power efficiency. Among classical asynchronous design templates, the Bundled-Data (BD) one stands off for its capability to provide high performance, reduce power and achieve area results similar to that of synchronous designs. Unlike the more robust Quasi-Delay Insensitive (QDI) templates, another common class of templates to implement asynchronous circuits, BD circuits require the extensive use of Delay Elements (DEs) to guarantee correct functionality. However, all circuits are affected by Process, Voltage and Temperature (PVT) variations, including the Combinational Logic (CL) on BD imposing margin on delay elements. In addition, current designs use voltage scaling to improve power efficiency, which impacts the delay differently in CLs and DEs adding more margin in DEs. A new template based on BD called Blade uses resiliency concept as a hope to avoid the delay margin caused by PVT and voltage scaling. Although, the use of two delay elements will represents more margins and extra test time on final circuit. So, this work shows an analysis of delay elements behavior under voltage scaling and the impact on post-silicon tests. It introduces a new term to determine the voltage scaling impact on delay elements and also the comparison between the most used DEs on BD designs using this novel metric. An analysis of tests in BD and Blade templates are presented and the impact of voltage scaling in these designs is analyzed. Finally, a novel delay element is proposed focusing in margin reduction and reduction in test time for Blade template.