No description available.

A stress control design protocol was developed to minimize coal mine bumps, which are the explosive failure of highly stressed pillars. The protocol was developed for room-and-pillar retreat mining conducted with available continuous miner technology. The inability of existing coal pillar equations to accurately represent the wide total extraction pillars required, forced the development of the pseudoductile coal pillar strength model. A confined pillar core is assumed to reach a maximum stress when surrounded by a yielded perimeter. The width of the yielded perimeter is assumed to increase linearly with increased coalbed thickness. The pseudoductile model was employed in the development of supercritical and subcritical width section design criteria. The supercritical design procedure assumes an infinitely long pillar line, composed of uniformly sized pillars, extracted against an infinitely wide gob area. Tributary area theory was combined with a linear shear angle concept to estimate the loads applied to total extraction pillars adjacent to gob areas. The boundary element code MULSIM/NL was utilized in the development and implementation of a systematic subcritical design procedure to apply the stress shield concept to retreat room-and-pillar coal mining, under bump hazard. The complex distribution of gob side abutment load between the side abutment pillars and the chain pillars in the total extraction zone made computer simulation a necessity. Section layouts were determined for the mining of a 6 ft thick coalbed under overburden up to 2,200 ft thick. The sections consist of total extraction areas separated by continuous abutment pillars. A spreadsheet program LAYOUT was created to summarize and provide for efficient utilization of the bump control design protocol. Based on overburden thickness, coalbed thickness, abutment load linear shear angle, and pillar dimensions entered by the user, LAYOUT calculates a stability factor for the first and second pillar row outbye the expanding gob for supercritical width sections. If the overburden and coalbed thickness conditions do not allow a supercritical section design, LAYOUT develops a subcritical design. / Ph. D.

No description available.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-07-22T14:21:25Z No. of bitstreams: 1 RODRIGO COHEN MOTA NEMER - DISSERTAÇÃO PPGMAT 2009..pdf: 672180 bytes, checksum: 3d0bc35e60d8a10be8afb4955883dd64 (MD5) / Made available in DSpace on 2018-07-22T14:21:25Z (GMT). No. of bitstreams: 1 RODRIGO COHEN MOTA NEMER - DISSERTAÇÃO PPGMAT 2009..pdf: 672180 bytes, checksum: 3d0bc35e60d8a10be8afb4955883dd64 (MD5) Previous issue date: 2009-03 / Capes / O resumo foi escrito utilizando formulas e equações matemáticas e por este motivo não fora possível transcreve-lo aqui. Para a visualizar o resumo recomendamos o downloado do arquivo. / The abstract was written using mathematical formulas and equations and for this reason it was not possible to transcribe it here. To view the summary we recommend downloading the file.

Shock control bumps (SCBs) are considered promising flow control devices for transonic commercial aircraft. By generating a λ-shock structure, 2D SCBs offer large drag savings, but perform poorly when that structure breaks down off-design. Milder-performing 3D devices produce weak vortices, that may offer some boundary layer control, and SCBs also affect buffet via direct impact on shock motions and separation. To date however, design studies have largely ignored complications from the swept, spanwise-varying flows, so this thesis tackles the question of whether SCB arrays can offer useful benefits to the performance of transonic commercial aircraft. Using a numerical infinite-wing model, a simple rotation adaptation is shown to redress deficient on-design drag performance of 3D SCBs under swept flows. With the correct rotation (dependent on height, planform and spacing) bumps follow performance-design trends similar to those in unswept flow. With this knowledge, an array design method is developed to tailor 2D and 3D devices to local flow conditions on an aircraft model, aiming to maximise on-design drag performance. Careful infinite-wing setup means the influence of rotation and array height on performance is replicated on the aircraft. Predicted array designs achieve 74-87% of their estimated local drag savings. However, with wave drag being a smaller percentage of the total, the influence of arrays on lift is more significant and makes the optimal designs shorter than predicted. Strategies for improving off-design drag performance are then evaluated. Stagger, an alternating chordwise translation applied to 3D arrays, broadens operating range and lowers drag penalties by better accommodating off-design shock movements, but offers a less favourable trade-off against on-design drag than simply reducing the array height. However, a 2D array can always outperform a 3D on drag objectives. Lastly, buffet performance is inferred using steady indicators based on trailing edge pressure and shock location. These disagree regarding the impact on buffet onset, unresolvably due to a lack of validation data, but agree that arrays could alleviate flow development post-onset. Optimal array designs depend on prioritised objectives: considering buffet severity and on-design drag, tall 2D (or 3D) arrays; for buffet and minimum off-design drag penalties (similar to the motivation behind vortex generator application), 3D arrays of varying height and stagger. A simple flight fuel consumption model utilising the computed drag data shows that many arrays are neutral or offer small savings (up to 0.3%) across a range of mission profiles. While likely too small to merit application for solely drag purposes, this implies buffet benefits without cost to efficiency. Unsteady tests and proper assessment of buffet onset are needed to confirm this.

No description available.

<p>The future International Linear Collider (ILC) and Compact Linear Collider (CLIC) are intended for precision measurements of phenomena discovered at the Large Hadron Collider (LHC) and also for the discovery of new physics. In order to offer optimal conditions for such experiments, the new colliders must produce very-high-luminosity collisions at energies in the TeV regime.</p><p>Emittance growth caused by imperfections in the main linacs is one of the factors limiting the luminosity of CLIC and ILC. In this thesis, various emittance preservation and luminosity tuning techniques have been tested and developed in order to meet the challenging luminosity requirements.</p><p>Beam-based alignment was shown to be insufficient for reduction of emittance growth. Emittance tuning bumps provide an additional powerful preservation tool. After initial studies of tuning bumps designed to treat certain imperfections, a general strategy for design of optimised bumps was developed. The new bumps are optimal both in terms of emittance reduction performance and convergence speed. They were clearly faster than previous bumps and reduced emittance growth by nearly two orders of magnitude both for CLIC and ILC.</p><p>Time-dependent imperfections such as ground motion and magnet vibrations also limit the performance of the colliders. This type of imperfections was studied in detail, and a new feedback system for optimal reduction of emittance growth was developed and shown to be approximately ten times more efficient than standard trajectory feedbacks.</p><p>The emittance tuning bumps require fast and accurate diagnostics. The possibility of measuring emittance using a wide laserwire was introduced and simulated with promising results. While luminosity cannot be directly measured fast enough, it was shown that a beamstrahlung tuning signal could be used for efficient optimisation of a number of collision parameters using tuning bumps in the Final Focus System.</p><p>Complete simulations of CLIC emittance tuning bumps, including static and dynamic imperfections and realistic tuning and emittance measurement procedures, showed that an emittance growth six times lower than that required may be obtained using these methods.</p>

L’évolution de la microélectronique suit plusieurs axes notamment la miniaturisation des éléments actifs (réduction de taille des transistors), et l’augmentation de la densité d’interconnexion qui se traduisent par la loi de Gordon Moore qui prédit que la densité d'intégration sur silicium doublerait tous les deux ans. Ces évolutions ont pour conséquence la réduction des prix et du poids des composants. L’hybridation ou flip chip est une technologie qui s’inscrit dans cette évolution, elle consiste en l’assemblage de matériaux hétérogènes. Dans cette étude il s‘agit d’un circuit de lecture Silicium et d’un circuit de détection InP ou GaAs assemblés par l’intermédiaire d’une matrice de billes d’indium. La connexion flip chip est basée sur l’utilisation d’une jonction par plots métalliques de faibles dimensions qui permet de diminuer les pertes électriques (faible inductance et faible bruit), une meilleure dissipation thermique, une bonne tenue mécanique. Enfin elle favorise la miniaturisation avec l’augmentation de la compacité et de la densité d’interconnexion.Les travaux de thèse se concentrent sur deux axes principaux. Le premier concerne l’hybridation par brasure avec la technologie des billes d’indium par refusion, et le second concerne l’hybridation par pression à température ambiante (nano-scratch) par l’intermédiaire des nanostructures (Nano-fils d’or, Nano-fils ZnO). Ces travaux ont permis la réalisation d’un détecteur InGaAs avec extension visible de format TV 640*512 pixels au pas de 15 µm. Ces travaux ont également permis la validation mécanique de l’assemblage d’un composant de format double TV 1280*1024 pixels au pas de 10 µm par cette même méthode de reflow. Pour l’axe hybridation à froid, nos travaux ont permis la validation d’une méthode de croissance de nano-fils ZnO par une voix hydrothermique à basse température (<90°C). / Evolution of microelectronics follows several major roads, in particular the size decrease of active elements (reduction of size of transistors), better electrical performances, high I/O density and smaller size. This revolution has been predicted by Gordon Moore who suggested that integrated circuits would double in complexity every 24 months. As a consequence, this evolution induces both the reduction of prices and the weight of components.The term flip chip describes the method of electrically connecting the die to the package substrate. Flip chip microelectronic assembly is the direct electrical connection of face-down (or flipped) integrated circuit (IC) chips onto substrates, circuit boards, or carriers, using conductive bumps on the chip bond pads. Flip chip offers the highest speed electrical performance, reduces the delaying inductance and capacitance of the connection, Smallest Size Greatest I/O Flexibility, Most Rugged, high I/O density and Lowest Cost.This thesis work study concentrates on two main directions. The first one concerns hybridization by means of the technology of Indium bumps associated to a reflow process and the second one is about pressure induced hybridization at low temperature using nanostructures (Nano-scratch). In this work, we have developed a complete process to assemble a focal plane array format of 640 x 512 pixels with a pitch of 15 µm. These studies also allowed the mechanical validation of hybridization of a focal plane arrays 1280*1024 pixels with a pitch of 10 µm. Concerning alternative technologies to flip chip reflow, we introduced and demonstrate the relevance of a method of growth of ZnO nanorods using low temperature wet chemical growth and further hybridization at ambient temperature.

The future International Linear Collider (ILC) and Compact Linear Collider (CLIC) are intended for precision measurements of phenomena discovered at the Large Hadron Collider (LHC) and also for the discovery of new physics. In order to offer optimal conditions for such experiments, the new colliders must produce very-high-luminosity collisions at energies in the TeV regime. Emittance growth caused by imperfections in the main linacs is one of the factors limiting the luminosity of CLIC and ILC. In this thesis, various emittance preservation and luminosity tuning techniques have been tested and developed in order to meet the challenging luminosity requirements. Beam-based alignment was shown to be insufficient for reduction of emittance growth. Emittance tuning bumps provide an additional powerful preservation tool. After initial studies of tuning bumps designed to treat certain imperfections, a general strategy for design of optimised bumps was developed. The new bumps are optimal both in terms of emittance reduction performance and convergence speed. They were clearly faster than previous bumps and reduced emittance growth by nearly two orders of magnitude both for CLIC and ILC. Time-dependent imperfections such as ground motion and magnet vibrations also limit the performance of the colliders. This type of imperfections was studied in detail, and a new feedback system for optimal reduction of emittance growth was developed and shown to be approximately ten times more efficient than standard trajectory feedbacks. The emittance tuning bumps require fast and accurate diagnostics. The possibility of measuring emittance using a wide laserwire was introduced and simulated with promising results. While luminosity cannot be directly measured fast enough, it was shown that a beamstrahlung tuning signal could be used for efficient optimisation of a number of collision parameters using tuning bumps in the Final Focus System. Complete simulations of CLIC emittance tuning bumps, including static and dynamic imperfections and realistic tuning and emittance measurement procedures, showed that an emittance growth six times lower than that required may be obtained using these methods.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.