Integration of sensors and silicon-based electronics for harsh environment applications is driven by the automotive industry and the maturity of semiconductor processes that allow embedding sensitive elements onto the same chip without sacrificing the performance and integrity of the electronics. Sensor devices post-processed on top of electronics by surface micromachining allow the addition of extra functionality to the fabricated ICs and creating a sensor system without significant compromise of performance. Smart sensors comprised of sensing structures integrated with silicon carbide-based electronics are receiving attention from more industries, such as aerospace, defense and energy, due to their ability to operate in very demanding conditions. This thesis describes the design and implementation of a novel, integrated thin film temperature sensor that uses a half-bridge arrangement to measure thin film platinum sensitive elements. Processes have been developed to fabricate temperature insensitive thin film tantalum nitride resistors which can be combined with the platinum elements to form the temperature transducing bridge. This circuit was designed to be integrated with an existing silicon carbide-based instrumentation amplifier by post-CMOS processing and to be initially connected to the bond pads of the amplifier input and output ports. Thin films fabricated using the developed TaN and Pt processes have been characterized using resistive test structures and crystallographic measurements of blanket thin film layer samples, and the relationship between the measurement results obtained has been analyzed. An initial demonstration of temperature sensing was performed using tantalum nitride and platinum thin film resistor element chips which were fabricated on passivated silicon substrates and bonded into high temperature packages. The bridge circuit was implemented by external connections through a printed circuit board and the bridge output was connected to a discrete instrumentation amplifier to mimic the integrated amplifier. The temperature response of the circuit measured at the output of the amplifier was found to have sensitivity of 844 μV·°C–1 over the temperature range of 25 to 100 °C. Two integrated microfabrication process flows were evaluated in this work. The initial process provided a very low yield for contact resistance structures between TaN and Pt layers, which highlighted problems with the thin film platinum deposition process. Multiple improvement options have been identified among which removal of the dielectric layer separating TaN and Pt layers and thicker Pt film were considered and a redesign of both layout and the process flow has resulted in improved yield of platinum features produced directly on top of TaN features. Temperature sensitivity of the integrated sensor devices was found to depend significantly on parasitic elements produced by thin film platinum step coverage, the values of which were measured by a set of resistive test structures. A new microfabrication design has enabled the production of a group of integrated temperature sensors that had a sensitivity of 150.84 μV·°C–1 in the temperature range between 25 and 200 °C on one of the fabricated wafers while the best fabricated batch of sensors had a sensitivity of 1079.2 μV·°C–1.

Orientador: Fernanda Paula Collares Queiroz / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia de Alimentos / Made available in DSpace on 2018-08-14T13:53:18Z (GMT). No. of bitstreams: 1 Fontes_LucianaCristinaBrigatto_D.pdf: 6013554 bytes, checksum: 9dd45a450968a0fd95033fd89bdb37d1 (MD5) Previous issue date: 2009 / Resumo: O Brasil apresenta a maior produção de batata-doce do continente latino-americano. Uma alternativa interessante para a expansão da cultura e também devido a sua alta perecibilidade seria a utilização da batata-doce como chips que é um mercado que vem crescendo muito por se tratar de um produto de conveniência. O objetivo deste estudo foi desenvolver chips de batata-doce com mínima incorporação de óleo, pela otimização da tecnologia combinada dos pré-tratamentos: desidratação osmótica e aplicação de coberturas comestíveis, antes do processo de fritura por imersão em oleína ou estearina de palma. A estratégia utilizada foi a avaliação sequencial das seguintes etapas: (i) estudo da atuação de diferentes antioxidantes na prevenção de escurecimento enzimático do vegetal; (ii) estudo do efeito das condições operacionais e teor das soluções desidratantes e otimização do processo de desidratação osmótica; (iii) potencial de aplicação de coberturas comestíveis; (iv) otimização do processo de fritura em oleína ou estearina de palma; (v) efeito combinado da desidratação osmótica e coberturas comestíveis antes do processo de fritura e (vi) estudo da vida útil dos chips desenvolvidos. O processo de imersão de batata-doce em solução de metabissulfito de sódio 2,0% constitui-se no método mais eficiente como tratamento preliminar para a inibição do escurecimento enzimático. No processo de desidratação osmótica para chips de batata-doce, as melhores condições operacionais encontradas foram: (i) concentração de glicerol/CaCl2 de 30%/1% (p/p); (ii) concentração de xarope de glicose de 63,75%, (iii) temperatura de 48ºC e (iv) tempo de 120 minutos. De acordo com a caracterização das propriedades químicas e físicas, o filme de alginato é o mais indicado para ser aplicado como cobertura nos chips de batata-doce. No aspecto coloração após a fritura, o filme de metilcelulose é o mais indicado, pois praticamente não apresentou alteração de coloração após o processo de fritura. A otimização do processo de fritura de chips de batata-doce frito em oleína de palma visando à minimização do teor de óleo incorporado e de umidade indicou como condições mais adequadas: (i) temperatura de 160ºC e (ii) tempo de 3 minutos e 30 segundos. O desenvolvimento de chips de batata-doce com baixa incorporação de óleo foi possível devido aos processos combinados (pré-tratamentos) de desidratação osmótica e aplicação de cobertura comestível de metilcelulose, reduzindo em 55,75% a absorção de óleo após o processo de fritura. Os chips de batata-doce controle e tratamento apresentaram algumas diferenças estatisticamente significativas (p<0,05%) nas características físicas e físico-químicas com a estocagem do produto, no entanto, não foi detectada sensorialmente pelos provadores, fazendo com que os chips de batata-doce pudessem ser estocados por 60 dias sem perdas das características sensoriais. Os chips de batata-doce não submetidos aos pré-tratamentos (controle) apresentaram melhores características físicas, físico-químicas e sensoriais durante os 60 dias de estocagem, se comparado aos chips de batata-doce com baixo teor calórico. A textura foi o atributo que mais influenciou negativamente a aceitação e a intenção de compra dos chips de batata-doce. A textura rígida, possivelmente, esteja relacionada com a natureza do vegetal e espessura da fatia utilizada. O emprego de outros processos tecnológicos pode melhorar a textura deste produto, fazendo com que a aceitação e a intenção de compra aumentem / Abstract: Brazil is the greatest sweet potato producer in the Latin American continent. An interesting alternative for the expansion of the culture of this root, that would also help solve problems related to its highly perishable nature, could be the production of sweet potato chips, a market that is growing as a convenience product. The aim of this study was to develop sweet potato chips with minimal oil incorporation, through the optimization of the combined technology of the pre-treatments: osmotic dehydration and application of edible coatings before the process of frying by immersion in the palm olein and stearin. The strategy used was to evaluate the following sequential steps: (i) study the performance of different antioxidants in the prevention of enzymatic browning of vegetables, (ii) study the effect of operating conditions and content of dehydrate solutions and optimization of the process of osmotic dehydration; (iii) potential application of edible coatings, (iv) optimization of the process of frying in palm olein or stearin, (v) the combined effect of osmotic dehydration and edible coatings before the process of frying and (vi) study shelf life of chips.The process of immersion of sweet potato, in a solution of sodium metabisulphite, 2% is in the most efficient method for preliminary treatment and the inhibition of enzymatic browning. In the process of osmotic dehydration for sweetpotato chips, the best operating conditions were: (i) concentration of glicerol/CaCl2 of 30%/1% (w/w), (ii) concentration of glucose syrup of 63.75%, (iii) temperature of 48ºC and (iv) time of 120 minutes. According to the characterization of chemical and physical properties the film of alginate is the most suitable to be used as mulch in sweet-potato chips. On the color after frying, the film of methylcellulose is the most appropriate, because almost showed no change in color after the process of frying. The optimization of the process of frying sweet potato chips fried in palm olein in order to minimize the oil content and moisture showed incorporated as the most appropriate: (i) temperature of 160 ° C and (i i) time of 3 minutes and 30 seconds. The development chips sweet potato with low oil incorporation was possible due to the combined processes (pre-treatments) of osmotic dehydration and application of edible methylcellulose coating, reducing oil absorption by 55.75% after the frying process. The control and treated sweet potato chips showed some statistically significant differences (p<0,05%) in physical and physicochemical characteristics during storage of the product, but, they were not detected in the sensory analysis by the panelists, making it possible to store the sweet potato chips for 60 days without loss of sensory characteristics. Control sweet potato chips showed better characteristics, both in physical and physicochemical analyses, as in sensory analysis, during the 60 days of storage, compared to treated sweet potato chips. Texture was the attribute that showed greatest negative influence on the acceptance and purchase intention of chips sweet potato. The rigid texture may be due to the nature of the vegetable and to the slice thickness used. The use of technological processes could improve the texture of this product, increasing acceptance and purchase intention / Doutorado / Doutor em Tecnologia de Alimentos

Thermal and quantum fluctuations of the electromagnetic near field of atoms and macroscopic bodies play a key role in quantum electrodynamics (QED), as in the Lamb shift. They lead, e.g., to atomic level shifts, dispersion interactions (Van der Waals-Casimir-Polder interactions), and state broadening (Purcell effect) because the field is subject to boundary conditions. Such effects can be observed with high precision on the mesoscopic scale which can be accessed in micro-electro-mechanical systems (MEMS) and solid-state-based magnetic microtraps for cold atoms (‘atom chips’). A quantum field theory of atoms (molecules) and photons is adapted to nonequilibrium situations. Atoms and photons are described as fully quantized while macroscopic bodies can be included in terms of classical reflection amplitudes, similar to the scattering approach of cavity QED. The formalism is applied to the study of nonequilibrium two-body potentials. We then investigate the impact of the material properties of metals on the electromagnetic surface noise, with applications to atomic trapping in atom-chip setups and quantum computing, and on the magnetic dipole contribution to the Van der Waals-Casimir-Polder potential in and out of thermal equilibrium. In both cases, the particular properties of superconductors are of high interest. Surface-mode contributions, which dominate the near-field fluctuations, are discussed in the context of the (partial) dynamic atomic dressing after a rapid change of a system parameter and in the Casimir interaction between two conducting plates, where nonequilibrium configurations can give rise to repulsion. / Thermische und Quantenfluktuationen des elektromagnetischen Nahfelds von Atomen und makroskopischen Körpern spielen eine Schlüsselrolle in der Quantenelektrodynamik (QED), wie etwa beim Lamb-Shift. Sie führen z.B. zur Verschiebung atomarer Energieniveaus, Dispersionswechselwirkungen (Van der Waals-Casimir-Polder-Wechselwirkungen) und Zustandsverbreiterungen (Purcell-Effekt), da das Feld Randbedingungen unterliegt. Mikroelektromechanische Systeme (MEMS) und festkörperbasierte magnetische Fallen für kalte Atome (‘Atom-Chips’) ermöglichen den Zugang zu mesoskopischen Skalen, auf denen solche Effekte mit hoher Genauigkeit beobachtet werden können. Eine Quantenfeldtheorie für Atome (Moleküle) und Photonen wird an Nichtgleichgewichtssituationen angepasst. Atome und Photonen werden durch vollständig quantisierte Felder beschrieben, während die Beschreibung makroskopischer Körper, ähnlich wie im Streuformalismus (scattering approach) der Resonator-QED, durch klassische Streuamplituden erfolgt. In diesem Formalismus wird das Nichtgleich- gewichts-Zweiteilchenpotential diskutiert. Anschließend wird der Einfluss der Materialeigenschaften von normalen Metallen auf das elektromagnetische Oberflächenrauschen, das für magnetische Fallen für kalte Atome auf Atom-Chips und für Quantencomputer-Anwendungen von Bedeutung ist, sowie auf den Beitrag des magnetischen Dipolmoments zum Van der Waals-Casimir-Polder-Potential im thermisch- en Gleichgewicht und in Nichtgleichgewichtssituationen untersucht. In beiden Fällen sind die speziellen Eigenschaften von Supraleitern von besonderem Interesse. Beiträge von Oberflächenmoden, die die Feldfluktuationen im Nahfeld dominieren, werden im Kontext des (partiellen) dynamischen Dressing nach einer raschen Änderung eines Systemparameters sowie für die Casimir-Wechselwirkung zweier metallischer Platten diskutiert, zwischen denen in Nichtgleichgewichtssituationen Abstoßung auftreten kann.

SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a testplan that identifies the conditions to be verified, (ii) a testcase that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and reused. In this work we present a methodology to synthesize testcases from reusable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of testcases, (ii) identifying code segments of testcases that can be reused from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the testcase, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize testcases. We discuss two specific classes of testcases. These are testcases for verifying the memory modules and the testcases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype testcase generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of testcases automatically that are correct by construction and (ii) reuse of the testcase code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.

Abstract des Vortrages: The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered. In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.

In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85°C) is determined. The cooling system is tested for varying values of applied power in the range of 15-40W. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77°C for a heat source of 40W, which is below the recommended electronic chips temperature of not exceeding 85°C. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.

Abstract des Vortrages: The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered. In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.

In this investigation, a single phase fluid is used to study the coupling between natural convection heat transfer within an enclosure and forced convection through computer covering case to cool the electronic chip. Two working fluids are used (water and air) within a rectangular enclosure and the air flow through the computer case is created by an exhaust fan installed at the back of the computer case. The optimum enclosure size configuration that keeps a maximum temperature of the heat source at a safe temperature level (85℃) is determined. The cooling system is tested for varying values of applied power in the range of 15−40𝑊. The study is based on both numerical models and experimental observations. The numerical work was developed using the commercial software (ANSYS-Icepak) to simulate the flow and temperature fields for the desktop computer and the cooling system. The numerical simulation has the same physical geometry as those used in the experimental investigations. The experimental work was aimed to gather the details for temperature field and use them in the validation of the numerical prediction. The results showed that, the cavity size variations influence both the heat transfer process and the maximum temperature. Furthermore, the experimental results ii compared favourably with those obtained numerically, where the maximum deviation in terms of the maximum system temperature, is within 3.5%. Moreover, it is seen that using water as the working fluid within the enclosure is capable of keeping the maximum temperature under 77℃ for a heat source of 40𝑊, which is below the recommended electronic chips temperature of not exceeding 85℃. As a result, the noise and vibration level is reduced. In addition, the proposed cooling system saved about 65% of the CPU fan power.

In this dissertation, mesoporous silica thin films with tunable features at the nanoscale were fabricated using the triblock copolymer template pathway, with the aim of specifically harvesting the low molecular weight peptides and proteins from human serum, which has been regarded as a potential source of diagnostic biomarkers for the early detection of disease. The superior properties of mesoporous silica have been demonstrated in applications which include chemical sensing, filtration, catalysis, drug-delivery and selective biomolecular uptake. These properties depend on the architectural, physical and chemical properties of the materials, which in turn are determined by the processing parameters in evaporation-induced self-assembly (EISA). Using the different polymer templates and polymer concentration in the precursor solution, various pore size distributions, pore structures and surface hydrophilicities were obtained and applied for nanotexture-selective recovery of low mass proteins. With the assistance of mass spectrometry and statistic analysis, we demonstrated the correlation between the nanophase characteristics of the mesoporous silica thin film and the specificity and efficacy of low mass proteome harvesting. In addition, to overcome the limitations of the pre-functionalization method in polymer selection, plasma ashing was used for the first time for the treatment of the mesoporous silica surface prior to chemical modification. Opposite surface charges due to the different functional groups used, resulted in a distinctive selectivity of the low molecular weight proteins from the serum sample. The mesoporous silica chips operate with extraordinary rapidity, high reproducibility, no sample pre-processing, and substantial independence from sample acquisition and storage temperature.In conclusion our study demonstrates that the ability to tune the physicochemical properties of mesoporous silica surfaces has the potential to promote the use of this material as a tool for the selective separation and concentration of the low molecular weight proteome from complex biological fluids. / text

Šiame darbe pateikta gluosninių žilvičių auginimo, ruošimo bei naudojimo analitinė apžvalga, gluosnių auginimo technikos ir technologijų energetinis vertinimas, nesubrendusių gluosnių pjaustinio ilgio teoriniai tyrimai naudojant žolinių augalų smulkintuvą. Taip pat eksperimentiškai nustatytos gluosnių fizikinės – mechaninės savybės, poveikis aplinkai deginant skirtingo pjaustinio gluosnius. Tyrimai atlikti naudojant 10 kW biokuro katilą, skirtą kūrenti energetinių augalų skiedroms, briketams, paletėms. Nustatytos kenksmingų medžiagų (CO2 , CO, NO, NOx) emisijos į aplinką deginant skirtingo tipo smulkintuvais susmulkintus gluosnius. / In this work the willow cultivation, preparation and use of analytical review of willows growing energy technology and technology assessment in juvenile willow cuttings-length adaptation of the theoretical studies of herbaceous plants shredder. It is well established experimentally rushes physical - mechanical properties of the environmental impact of combustion of different willow cuttings. Investigations were carried out using a 10 kW biofuel boiler to burn energy crops for wood chips, briquettes, pallets. Down (CO2 , CO, NO, NOx) emissions into the environment by burning different types of chopped willow cutter.