O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm. / In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.

Abstract A stripline structure is closed and therefore protected against surrounding EMI and it is easy to bury in multiplayer structures, which offer higher circuit density. This thesis focuses on the evaluation (and verification via actual structures) of the correct simulation of striplines and, as a new aspect, the advantages of using a dual-stripline. Multiple design methods and electromagnetic simulation systems were tested and properties of these are compared. For a reliable design it is still necessary to use at least two tools, at first a very fast tool having excellent circuit parameter optimization methods and then some electromagnetic simulator, which can be used to the complete the realizable layout. That is, because all the electromagnetic simulators suffer from the same limiting factors, the memory capacity of the computer and the unacceptable calculation time. It has been discovered through modelling that the "cat-eye" shape having many more and larger local inaccuracies at the thinned edge areas of the sintered conductor in LTCC structures increases the conductor losses. Therefore it is important to develop new manufacturing methods capable of producing better-shaped conductors. A combination of broadside coupled parallel connected striplines has been tested both in High Temperature Superconducting ( HTS ) and LTCC materials. A two-conductor stripline, a dual stripline, raises the power handling capability of a microwave bandpass HTS filter. In addition, it offers the possibility to use a normal metal protection layer at the surface of the superconductor without degradation of electrical properties, thus increasing the power handling capability even more. The dual stripline solution in LTCC would offer some preferable properties in high power filters only. The shape of the ground plane used for trimming the coupling between resonators was also found to have a remarkable influence on the quality factor of the resonator. A quite narrow ground strip can offer a much better quality factor with the same coupling level than a meshed or continuous ground plane, but it requires accurate design and manufacturing methods. It would help to design filters with lower loss in the passband without compromises in the attenuation outside the passband.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22658号 / 工博第4742号 / 新制||工||1741(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 篠原 真毅, 教授 守倉 正博, 教授 小嶋 浩嗣 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

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No description available.

This thesis involves the creation of a system of embedded touchscreen devices called touchSPICE to aid in the learning of basic circuits. Traditionally, circuit theory is taught to students in two different methods, lectures and laboratory exercises. Lectures focus on auditory and visual learning and are largely passive learning. Lab experiments allow students to physically interact with the circuits, and learn visually through viewing output waveforms from simulators or on measurement devices. The goal of the touchSPICE project is to develop a physical system for virtual, real-time SPICE simulation that mimics the laboratory experience. In touchSPICE, touchscreen devices act as circuit nodes that communicate with immediate neighbors using physical wires. Additionally, the nodes communicate wirelessly with a host computer, running a customized version of SPICE. Data is aggregated on the host computer and plotted in real-time. Changes in configuration of the nodes (component types and values), are then reflected on the host computer’s display. The efficacy of touchSPICE as a learning tool was evaluated by using anonymous surveys from 20 subjects including a pretest, followed by an interactive session with touchSPICE, and a follow-up posttest. Results collected showed that with a few changes to improve the responsiveness of the touchscreen, touchSPICE may be an effective method for teaching circuit theory. Additionally, users enjoyed the quick configuration time that touchSPICE provided, and felt that the real-time feedback of touchSPICE helped support understanding of how circuits operate.

Light-emitting diodes (LEDs) offer energy-efficient lighting and are widely adopted. However, LED drivers that regulate power can fail when subjected to voltage disturbances on the electrical grid. This research investigates how components within LED drivers durability when undergoing voltage impulses and swells using simulation-based methods. An LED driver circuit was modeled in LTspice circuit simulation software. Impulses from 35-65V and equivalent voltage swells were applied to the simulated driver. The electrical stresses on components were statistically analyzed using the design of experiments and general full factorial. This methodology identified the most vulnerable components and their common durability/failure mechanisms during impulse and swell events. The findings provide insights into design changes that harden drivers against grid disturbances. This study determines that higher capacitor voltage ratings improved voltage impulse and swell withstand. Additionally, adding a surge suppression diode across the LED minimized diode reverse breakdown during swells. This simulation-based approach enables the informed design of robust LED drivers that can withstand electrical grid perturbations through strategic hardening of the most vulnerable components. The methodology and findings provide a framework for the reliability optimization of LED drivers and other power electronic systems exposed to power quality disturbances.Keywords: LED driver, voltage disturbance, component failure, circuit simulation, design of experiments (DOE), general full factorial.

Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-08-31Bitstream added on 2014-06-13T20:29:09Z : No. of bitstreams: 1 lima_val_me_ilha.pdf: 399126 bytes, checksum: 5597e5f619ca9aa5e433432ef064a3bf (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / O objetivo deste trabalho é o desenvolvimento de uma arquitetura reconfigurável estaticamente, de um elemento de processamento (MPH) para o ambiente de simulação de circuitos ABACUS. Este elemento de processamento consiste de um conjunto de unidades funcionais que podem ser relacionadas por meio de algumas palavras de controle armazenadas na ROM, e cuja interconexão pode ser alterada para que o hardware de processamento se adapte ao modelo do elemento de circuito a ser simulado. O projeto foi descrito em linguagem VHDL e simulado com o auxílio do software QUARTUS II. / The aim of this work is the development of a statically reconfigurable architecture, of a processing element (MPH) for the ABACUS circuit simulation environment. This processing element consists of a set of functional units that can be related by means of some control words stored in the ROM, and whose interconnection can be modified so that the processing hardware be adapted to the model of the circuit element to be simulated. The project was described in VHDL, and simulated with the aid of Quartus II software.

In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics in order to quantify their performance and identify efficient circuit simulators. In addition, I designed a sigma-delta modulator and its individual components using the analog behavioral language Verilog-A. Initially, I performed simulations of individual components of the sigma-delta modulator and later of the whole system. Finally, CMOS (complementary metal-oxide semiconductor) transistor-level circuits were designed for the differential amplifier, operational amplifier and comparator of the modulator.

京都大学 / 新制・課程博士 / 博士(工学) / 甲第23207号 / 工博第4851号 / 新制||工||1757(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 篠原 真毅, 教授 守倉 正博, 准教授 久門 尚史 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM