A melatonina, produzida pela pineal e secretada de maneira cíclica num período de 24 horas, possui ação na sincronização dos ritmos biológicos. Admitindo-se que a expressão circadiana dos clock genes está envolvida na regulação do metabolismo energético e que este padrão oscilatório está sob influência da melatonina, avaliamos o processo de incorporação de glicose em lipídeos no tecido adiposo de ratos controles e pinealectomizados e verificamos a interferência da pinealectomia na expressão dos genes relógio. Os resultados mostram que a pinealectomia alterou a expressão circadiana dos genes Clock, Per2 e Cry1, aumentou a expressão de Rev-erb (Zt 8) e alterou a expressão de Ppar. Ainda, provocou aumento nas concentrações séricas de corticosterona e diminuição nas de leptina. No entanto, o processo de incorporação de glicose em lipídeos não foi alterado. Sendo assim, concluímos que apesar da pinealectomia ter afetado eventos moleculares e metabólicos, quatro semanas de cirurgia ainda é curto para evidenciar repercussões metabólicas mais significativas no animal. / Melatonin, which is produced by pineal gland and secreted in a cyclic fashion over 24 hours, acts in biological rhythms synchronization. Thus, assuming that circadian expression of clock genes is involved in the regulation of energy metabolism and that oscillatory pattern is under influence of melatonin, we analyzed the process of glucose incorporation into lipids in adipose tissue of pinealectomized and controls rats and we determined whether pinealectomy interferes on the expression of clock genes in this tissue. Our results show that pinealectomy alters the circadian pattern of Clock, Per2, Cry1 and Ppar expression, while increases the Rev-erb gene expression (Zt 8). Moreover, the pinealectomy promoted increased corticosterone and decreased leptin plasma levels. However, the incorporation of glucose into lipids over 24 hours was not altered by pinealectomy. Thus, we conclude that despite the pinealectomy have affected molecular and metabolic events, four weeks of surgery is still too short to induce more significant metabolic effects in animals.

Thesis (M.B.A.)--Chinese University of Hong Kong. / Bibliography: leaves 82-83.

Variações ambientais e de processo representam um grande desafio a ser vencido pelas redes de distribuição de relógio. O efeito das variações nos atrasos da rede de distribuição de relógio não pode ser previsto com precisão e portanto não podem ser diretamente considerados no projeto das redes de distribuição de relógio. Estruturas baseadas em clock meshes (i.e. clock mesh, clock spines e crosslinks) são a maneira mais eficiente de proteger a rede de relógio do efeito das variações nos atrasos. Clock meshes tem sido utilizados por bastante tempo no projeto de microprocessadores e recentemente foram incluídos no fluxo de síntese de ASICs. Embora o uso de clock meshes esteja aumentando há uma grande necessidade por métodos de analise e otimização dos mesmos. Essa tese propõe soluções para ambos os problemas. Uma metodologia para permitir a simulação elétrica de clock meshes grandes é proposta. O método proposto permite que a simulação dos clock meshes seja paralelizada com um erro menor que 1%. Duas metodologias de otimização também são propostas nessa tese. A primeira consiste em um algoritmo para dimensionamento para os mesh buffers. Esse algoritmo permite que o clock skew e o consumo de potência sejam reduzidos ao custo de aumentar o clock slew. O segundo método de otimização proposto consiste em um novo projeto para os mesh buffers. O novo mesh buffer é capaz de reduzir o clock skew em 22% e o consumo de potencia em 59%. / Process and environmental variations are a great challenge to clock network designers. Variations effect on the clock network delays can not be predicted, hence it can not be directly accounted in the design stage. Clock mesh-based structures (i.e. clock mesh, clock spines and crosslinks) are the most effective way to tolerate variation effects on delays. Clock meshes have been used for a long time in microprocessor designs and recently became supported by commercial tools in the ASIC design flow. Although clock meshes have been known for some time and its use in ASIC design is increasing, there is a lack of good analysis and optimization strategies for clock meshes. This thesis tackles both problems. Chapter 1 presents a basic introduction to clock distribution and important definitions. A review of existent clock dsitribution design strategies is presented in chapter 2. A study about the clock distribution architecture used in several microprocessor and a comparison between mesh-based and pure tree clock distribution architectures is shown in chapter 3.2. A methodology for enabling and speeding up the simulation of large clock meshes is presented in chapter 4. The proposed analysis methodology was shown to enable the parallel evaluation of large clock meshes with an error smaller than 1%. Chapter 5 presents two optimization strategies, a new mesh buffer design and a mesh buffer sizing algorithm. The new mesh buffer design was proposed improving clock skew by 22% and clock power by 59%. The mesh buffer sizing algorithm can reduce clock skew by 33%, power consumption by 20% with at the cost of a 26% slew increase. At last conclusions are presented on chapter 6.

Thesis on the subject of lasercooling and trapping of neutral mercury for the purpose of making a lattice clock.

ElectroMagnetic Interferences (EMI) are emerging problems in today's high speed circuits. There are several examples that these interferences affected the circuits and systems. This work tries to reduce the abovementioned problems in synchronous systems by modifying the clock signal such that it produces less interferers. In this thesis first EMI and its sources and related definitions are studied in Chap.1 and then a theoretical background is presented in Chap.2, finally Chap.3 and Chap.4 are dedicated to circuit implementation and simulation results, respectively. A novel multi-segment clocking scheme is presented in this thesis. An analytical methods for formal verification of advantages of this clocking method is presented in Chap.2. Chap.3 and Chap.4 also are devoted to implementation, simulation and comparison of proposed clocking method versus other methods. Since proposed clocking method does not set any constraint on timing (speed of the circuit) and does not impose very high extra power consumption on the circuit, compared to the conventional clocking, this method could be used to reduce interferences in system.

As part of the ongoing world-wide effort in improving time and frequency references, a high accuracy optical frequency standard was developed using the electric quadrupole allowed clock transition at 445 THz (674 nm) in a trapped and laser cooled 88Sr+ion. An ion trap system of the endcap design has been recently evaluated with a fractional frequency uncertainty which surpasses the accuracy of the current realization of the SI second. This thesis seeks to further evaluate the limiting systematic shifts of the device by optimizing a second ion trap reference based on a rf Paul trap design, which was then compared with the endcap trap reference frequency. The comparison of the two ion traps' reference frequencies confirmed an overall offset of -0.36 pm 0.08 Hz at the 445 THz reference frequency corresponding to a fractional frequency offset of 8 x 10^-16.

Wireless networks become more and more important in modern information systems as the last mile/meter solutions, thanks to the flexibility of mobile access to facilitate Internet access anytime, anywhere. Given the limited resources, e.g., spectrum and energy supplies, to meet the ever increasing demand for wireless data services, new approaches are beckoned to enhance the spectrum and energy efficiency. We investigate this problem from three important aspects, digital modulation, clock synchronization and concurrent transmission scheduling. The contributions of this dissertation are four-fold. First, we employ the cross-layer design to explore the spatial diversity and broadcast nature of wireless links and propose a novel network modulation scheme that can superpose the information bits of different priorities into one symbol. It offers a new dimension to improve the network throughput since we can flexibly configure the transmission according to the channels among transceivers. Moreover, it is compatible with the main-stream hardware and we just need a software upgrade to implement the idea. Second, we propose modulation schemes based on hexagonal tiling, which is known to be the most compact way of two-dimensional regular tiling. In order to fully utilize the advantage of hexagonal constellation, we employ the non-binary error controlcoding since the number of constellation points of hexagonal constellation is not necessarily to be an integer power-of-two. The feasibility of these new modulation schemes is verified by the prototype system based on the software defined radio platform USRP2 and GNU Radio. Third, to facilitate a wide range of wireless communications technologies and protocols, clock synchronization among several wireless devices is a fundamental requirement. We investigated this problem by tracing to the source of clock desynchronization, which is the clock skew. However, as shown by measurement results, the clock skew is not constant and related to the working temperature. We propose a novel clock skew estimation algorithm that can leverage the temperature information to accurately estimate the clock skew. Based on the estimation results, we propose a clock synchronization scheme that can directly remove the clock skew according to the working temperature. Fourth, the traditional time-sharing based scheduling schemes usually schedule one transmission within certain area. The emerging broadband wireless devices can dynamically adjust the transmitted data rate according to the received signal to interference and noise ratio (SINR). Allowing concurrent transmissions may be more efficient, while optimal scheduling problem for concurrent transmissions is an NP-hard problem. We propose simple yet effective heuristic algorithms that can significantly improve the system throughput with moderate computational complexity. / Graduate / 0544 / yangzhe2007@gmail.com

Variações ambientais e de processo representam um grande desafio a ser vencido pelas redes de distribuição de relógio. O efeito das variações nos atrasos da rede de distribuição de relógio não pode ser previsto com precisão e portanto não podem ser diretamente considerados no projeto das redes de distribuição de relógio. Estruturas baseadas em clock meshes (i.e. clock mesh, clock spines e crosslinks) são a maneira mais eficiente de proteger a rede de relógio do efeito das variações nos atrasos. Clock meshes tem sido utilizados por bastante tempo no projeto de microprocessadores e recentemente foram incluídos no fluxo de síntese de ASICs. Embora o uso de clock meshes esteja aumentando há uma grande necessidade por métodos de analise e otimização dos mesmos. Essa tese propõe soluções para ambos os problemas. Uma metodologia para permitir a simulação elétrica de clock meshes grandes é proposta. O método proposto permite que a simulação dos clock meshes seja paralelizada com um erro menor que 1%. Duas metodologias de otimização também são propostas nessa tese. A primeira consiste em um algoritmo para dimensionamento para os mesh buffers. Esse algoritmo permite que o clock skew e o consumo de potência sejam reduzidos ao custo de aumentar o clock slew. O segundo método de otimização proposto consiste em um novo projeto para os mesh buffers. O novo mesh buffer é capaz de reduzir o clock skew em 22% e o consumo de potencia em 59%. / Process and environmental variations are a great challenge to clock network designers. Variations effect on the clock network delays can not be predicted, hence it can not be directly accounted in the design stage. Clock mesh-based structures (i.e. clock mesh, clock spines and crosslinks) are the most effective way to tolerate variation effects on delays. Clock meshes have been used for a long time in microprocessor designs and recently became supported by commercial tools in the ASIC design flow. Although clock meshes have been known for some time and its use in ASIC design is increasing, there is a lack of good analysis and optimization strategies for clock meshes. This thesis tackles both problems. Chapter 1 presents a basic introduction to clock distribution and important definitions. A review of existent clock dsitribution design strategies is presented in chapter 2. A study about the clock distribution architecture used in several microprocessor and a comparison between mesh-based and pure tree clock distribution architectures is shown in chapter 3.2. A methodology for enabling and speeding up the simulation of large clock meshes is presented in chapter 4. The proposed analysis methodology was shown to enable the parallel evaluation of large clock meshes with an error smaller than 1%. Chapter 5 presents two optimization strategies, a new mesh buffer design and a mesh buffer sizing algorithm. The new mesh buffer design was proposed improving clock skew by 22% and clock power by 59%. The mesh buffer sizing algorithm can reduce clock skew by 33%, power consumption by 20% with at the cost of a 26% slew increase. At last conclusions are presented on chapter 6.

Variações ambientais e de processo representam um grande desafio a ser vencido pelas redes de distribuição de relógio. O efeito das variações nos atrasos da rede de distribuição de relógio não pode ser previsto com precisão e portanto não podem ser diretamente considerados no projeto das redes de distribuição de relógio. Estruturas baseadas em clock meshes (i.e. clock mesh, clock spines e crosslinks) são a maneira mais eficiente de proteger a rede de relógio do efeito das variações nos atrasos. Clock meshes tem sido utilizados por bastante tempo no projeto de microprocessadores e recentemente foram incluídos no fluxo de síntese de ASICs. Embora o uso de clock meshes esteja aumentando há uma grande necessidade por métodos de analise e otimização dos mesmos. Essa tese propõe soluções para ambos os problemas. Uma metodologia para permitir a simulação elétrica de clock meshes grandes é proposta. O método proposto permite que a simulação dos clock meshes seja paralelizada com um erro menor que 1%. Duas metodologias de otimização também são propostas nessa tese. A primeira consiste em um algoritmo para dimensionamento para os mesh buffers. Esse algoritmo permite que o clock skew e o consumo de potência sejam reduzidos ao custo de aumentar o clock slew. O segundo método de otimização proposto consiste em um novo projeto para os mesh buffers. O novo mesh buffer é capaz de reduzir o clock skew em 22% e o consumo de potencia em 59%. / Process and environmental variations are a great challenge to clock network designers. Variations effect on the clock network delays can not be predicted, hence it can not be directly accounted in the design stage. Clock mesh-based structures (i.e. clock mesh, clock spines and crosslinks) are the most effective way to tolerate variation effects on delays. Clock meshes have been used for a long time in microprocessor designs and recently became supported by commercial tools in the ASIC design flow. Although clock meshes have been known for some time and its use in ASIC design is increasing, there is a lack of good analysis and optimization strategies for clock meshes. This thesis tackles both problems. Chapter 1 presents a basic introduction to clock distribution and important definitions. A review of existent clock dsitribution design strategies is presented in chapter 2. A study about the clock distribution architecture used in several microprocessor and a comparison between mesh-based and pure tree clock distribution architectures is shown in chapter 3.2. A methodology for enabling and speeding up the simulation of large clock meshes is presented in chapter 4. The proposed analysis methodology was shown to enable the parallel evaluation of large clock meshes with an error smaller than 1%. Chapter 5 presents two optimization strategies, a new mesh buffer design and a mesh buffer sizing algorithm. The new mesh buffer design was proposed improving clock skew by 22% and clock power by 59%. The mesh buffer sizing algorithm can reduce clock skew by 33%, power consumption by 20% with at the cost of a 26% slew increase. At last conclusions are presented on chapter 6.

Current models state that insect peripheral oscillators are directly responsive to light, while mammalian peripheral clock genes are coordinated by a master clock in the brain via intermediate factors, possibly hormonal. We show that the expression levels of two circadian clock genes, period (per) and Par Domain Protein 1 (Pdp1) in the peripheral tisue of an insect model species are inversely affected by contrasting photoperiods. The effect of photoperiod on per and Pdp1 mRNA levels was found to be mediated by the juvenile hormone. Our results provide the first experimental evidence for hormonal regulation of circadian clock gene expression in insects.