Non-uniformity in chemical-mechanical planarization (CMP) due to diverse pattern geometry in copper damascene structures has been a critical limit to process yield. Fundamental understanding in tribology and electrochemistry is crucial to solve this problem. This research develops novel triboelectrochemical techniques to characterize the polished wafer surface and to understand mechanisms of materials removal. There are two approaches in this research. Experimentally, a setup containing a tribometer and a potentiostat was built. It enabled simultaneous measurement in friction coefficient and electrochemical response of wafer materials. Theoretically, electrochemical reactions and Hertzian contact were analyzed on ECMPed wafers in terms of mechanisms of step height reduction in anodic and cathodic ECMP in corresponds to surface chemistry. Results revealed the nature of limitation of ECMP for global planarization. In order to further the fundamental investigation of ECMP, the potentiostatic electrochemical impedance spectroscopy (EIS) was utilized to study the interface kinetics. It was revealed that the formation of Cu oxide films was affected by the electrical potentials. Through in situ measurement, it was found that the tribological behavior depend on the surface chemistry and surface morphology under the influence of anodic potentials. The potentiodynamic polarization results explained the removal and formation mechanisms of interface. The results showed that the cycle of passivation/removal was a function of mechanical factor such as the load and speed. The new model was developed via material removal rate (MRR) in both electrochemical and mechanical aspects. The quantitative contribution of electrochemical potential to overall removal was established for the first time. It was further confirmed by Ru and the electrochemical constant j was developed for metal ECMP. This dissertation includes seven chapters. Chapter I Introduction and II Motivation and Objectives are followed by the materials setup and testing conditions discussed in Chapter III. The tribological and electrochemical characterization of the Cu patterned geometry is discussed in Chapter IV. Chapter V discusses the kinetics of the interface during polishing and its removal mechanisms. Chapter VI discusses the synergism of ECMP, followed by Conclusions and Future work.

Copper based interconnects with low dielectric constant layers are currently used to increase interconnect densities and reduce interconnect time delays in integrated circuits. The technology used to develop copper interconnects involves Chemical Mechanical Planarization (CMP) of copper films deposited on low-k layers (silica or silica based films), which is carried out using slurries containing abrasive particles. One issue using such a structure is copper contamination over dielectric layers (SiO2 film), if not reduced, this contamination will cause current leakage. In this study, the conditions conducive to copper contamination onto SiO2 films during Cu-CMP process were studied, and a post-CMP cleaning technique was discussed based on experimental results. It was found that the adsorption of copper onto a silica surface is kinetically fast (< 0.5 minute). The amount of copper absorbed is pH and concentration dependent and affected by presence of H2O2, complexing agents, and copper corrosion inhibitor Benzotrazole. Based on de-sorption results, DI water alone was unable to reduce adsorbed copper to an acceptable level, especially for adsorption that takes place at a higher pH condition. The addition of complex agent, citric acid, proved effective in suppressing copper adsorption onto oxide silica during polishing or post-CMP cleaning by forming stable copper-CA complexes. Surface Complexation Modeling was used to simulate copper adsorption isotherms and predict the copper contamination levels on SiO2 surfaces.Another issue with the application of copper CMP is its environmental impact. CMP is a costly process due to its huge consumption of pure water and slurry. Additionally, Cu-CMP processing generates a waste stream containing certain amounts of copper and abrasive slurry particles. In this study, the separation technique electrocoagulation was investigated to remove both copper and abrasive slurry particles simultaneously. For effluent containing ~40 ppm dissolved copper, it was found that ~90% dissolved copper was removed from the waste streams through electroplating and in-situ chemical precipitation. The amount of copper removed through plating is impacted by membrane surface charge, type/amount of complexing agents, and solid content in the slurry suspension. The slurry particles can be removed ~90% within 2 hours of EC through multiple mechanisms.

<p>There is seemingly a never-ending consumer demand for mobileterminals such as cellular phones and personal digitalassistants (PDAs). Each new generation of terminals comes withmore elaborate functions than in the previous generation. Thistrend results in a higher performance demand on the computerarchitecture that performs the required computations within theterminal. To satisfy the projected requirements on cominggenerations of mobile terminals, we propose an architecturethat when intelligently managed can provide the necessaryperformance at low power and energy consumption. Thisarchitecture, a chip-multiprocessor (CMP), thus amulti-processor implemented on a single chip, has incombination with adaptive scheduling strategies the potentialto efficiently fullfill future requirements.</p><p>This licentiate thesis spans over several studies done onthe effectiveness of the adaptive CMP. In our studies, we haveshown that an adaptive CMP can satisfy the same performancerequirements as a comparable uni-processor, still consumingless power and energy. Furthermore, we have made an effort toaccurately model the workload behaviour of mobile terminals,which is of paramount importance when comparing candidatearchitectures. In the future, apart from proposing moreadaptive scheduling techniques, we expect to do more thoroughstudies on workload modeling as well as on the operating systeminfluence on the overall performance and power consumption.</p>

Long the dominant method of wafer planarization in the integrated circuit (IC) industry, chemical-mechanical polishing is starting to play an important role in microelectromechnical systems (MEMS). We present an experiment to characterize a polysilicon CMP process with the specific goal of examining MEMS sized test structures. We utilize previously discussed models and examine whether the same assumptions from IC CMP can be made for MEMS CMP. We find that CMP at the MEMS scale is not just pattern density dependent, but also partly dependent on feature size. Also, we find that new layout designs relevant to MEMS can negatively impact how well existing CMP models simulate polishing, motivating the need for further model development. / Singapore-MIT Alliance (SMA)

During the CMP process, a wafer is rotated and pressed face down against a rotating polishing pad. Polishing slurry is delivered on the top of pad continuously and forms a thin lubricating film between the wafer and the pad. In this study, a three-dimensional slurry flow model based on a generalized Reynolds equation is developed, which can apply to a rough pad with the compressibility of the pad, and the multi-grid method is used to reduce computational time. According to the force and moment balance equations, the tilted angles and the slurry film thickness can be evaluated. When the pad surface is rough, the squeeze term differentiated by time should be considered in this model due to the rotation of the pad. The influences of applied load, pad speed, wafer speed, pad compressibility, and surface roughness pattern on the tilted angles and the slurry film thickness are investigated. Results show that the variation of the tilted angles becomes more significant for the anisotropic than that for the isotropic during the rotation of the pad. And the slurry film thickness at the center of the wafer increases as applied load decreases or pad speed increases or wafer speed decreases or the compressibility of the pad increases.

In conventional abrasive machining , it must using dresser to dress the surface of polishing disc periodically , in order for polishing disc to maintain its ability of machining , and then ensuring the quality of work piece. It will make polishing disk thin , finally it must losing it ability of machining , and then be replaced by a new disc. For this reason , in the study , an idea of a new type ultraprecision polisher is proposed . Using Sn-Al2O3 composite coating to reach the mirror surface grinding of silicon wafer in the tin bath , and grinding with electroplating continuously . It will ensure the ability of machining of polishing disc . In the study , first , analyzing the effect of rotational speed rate of wafer and polishing disc on the grinding trajectories type of machining surface . From the result of analysis , find that , when the rotational speed rate is more irregular or it could not divided , the arrangement of grinding trajectories is more complex . And then , investigating the effect of cathode current density , rotational speed of polishing disc and time of plating on the characteristics of composite coating . In the experiment of composite electroplating , when cathode current density is higher , the size of crystal is smaller , the thickness of coating is thicker , and the quantity of Al2O3 within coating decrease lightly . The increase of the rotational speed of polishing disk could increase the size of crystal , the thickness of coating and the quantity of Al2O3 lightly . The time of plating is longer , the shape of crystal is more obvious , the thickness of coating is thicker and it also increase the quantity of Al2O3 . Finally , investigating the effect of cathode current density and cationic surfactant PEI on the characteristics of coating and wafer . In practical abrasive machining , the removal rate of wafer increases with cathode current density , and the addition of PEI could increase the quantity of Al2O3 indeed . Besides , under the same machining condition , in the tin bath with PEI , the removal rate is higher than the one in the tin bath without PEI .

Future processors will integrate an increasing number of cores because the scaling of single-thread performance is limited and because smaller cores are more power efficient. Off-chip memory bandwidth that is shared between those many cores, however, scales slower than the transistor (and core) count does. As a result, in many future systems, off-chip bandwidth will become the bottleneck of heavy demand from multiple cores. Therefore, optimally managing the limited off-chip bandwidth is critical to achieving high performance and efficiency in future systems. In this dissertation, I will develop techniques to optimize the shared use of limited off-chip memory bandwidth in chip-multiprocessors. I focus on issues that arise from the sharing and exploit the differences in memory access characteristics, such as locality, bandwidth requirement, and latency sensitivity, between the applications running in parallel and competing for the bandwidth. First, I investigate how the shared use of memory by many cores can result in reduced spatial locality in memory accesses. I propose a technique that partitions the internal memory banks between cores in order to isolate their access streams and eliminate locality interference. The technique compensates for the reduced bank-level parallelism of each thread by employing memory sub-ranking to effectively increase the number of independent banks. For three different workload groups that consist of benchmarks with high spatial locality, low spatial locality, and mixes of the two, the average system efficiency improves by 10%, 7%, 9% for 2-rank systems, and 18%, 25%, 20% for 1-rank systems, respectively, over the baseline shared-bank system. Next, I improve the performance of a heterogeneous system-on-chip (SoC) in which cores have distinct memory access characteristics. I develop a deadline-aware shared memory bandwidth management scheme for SoCs that have both CPU and GPU cores. I show that statically prioritizing the CPU can severely constrict GPU performance, and propose to dynamically adapt the priority of CPU and GPU memory requests based on the progress of GPU workload. The proposed dynamic bandwidth management scheme provides the target GPU performance while prioritizing CPU performance as much as possible, for any CPU-GPU workload combination with different complexities. / text

Στη διπλωματική αυτή υλοποιήσαμε την παράλληλη αρχιτεκτονική Pisma στο περιβάλλον εξομοίωσης Simics. Η αρχιτεκτονική PiSMA αφορά τη διασύνδεση επεξεργαστών και μνημών πάνω στο ίδιο τσιπ σε μορφή σκακιέρας έτσι ώστε κάθε επεξεργαστής να είναι συνδεδεμένος με τέσσερις μνήμες και κάθε μνήμη να είναι συνδεδεμένη με τέσσερις επεξεργαστές. Αυτή η διάταξη επιτρέπει σε κάθε επεξεργαστή να επικοινωνεί άμεσα διαμέσου των μνημών με οκτώ γειτονικούς του επεξεργαστές. Η επικοινωνία με κάποιον επεξεργαστή εκτός των οκτώ γειτονικών γίνεται με τη μετάδοση μηνυμάτων μεταξύ των μνημών. Η αρχιτεκτονική Pisma είναι επεκτάσιμη σε αυθαίρετο αριθμό επεξεργαστών και μνημών και το κύριο πλεονέκτημά της εμφανίζεται σε εφαρμογές που παρουσιάζουν μεγάλη τοπικότητα καθώς έτσι τα δεδομένα μπορούν να επεξεργαστούν από περισσότερους επεξεργαστές ταυτόχρονα ενώ παράλληλα μειώνεται και το overhead της μεταφοράς των δεδομένων μέσω των μνημών. Στη διπλωματική θα δοθεί επίσης περιγραφή της σύγχρονης, αξιόπιστης και ολοκληρωμένης πλατφόρμας εξομοίωσης Simics. Συγκεκριμένα θα περιγραφούν τα εργαλεία που προσφέρει για την υλοποίηση των διάφορων εξομοιώσεων μέσω των κλάσεων που διαθέτει, ο τρόπος λειτουργίας του και ποια συστήματα έχουν εξομοιωθεί και έχουν προστεθεί στο περιβάλλον μέχρι τώρα. / In this thesis we implemented the parallel PiSMA architecture on Simics simulator. The PiSMA architecture forms an expandable toroidal grid with alternating processors and memories so that its processor is connected to four memories and each memory to four processors. This structure enables every processor to communicate through the common memories to other eight adjacent processors. The communication between remote processors is performed by message passing. PiSMA architecture is scalable to hundreds of processors. The most important advantage of this new architecture is that it can process applications that can divide in independent granules more efficiently by mapping them to as much as many processors this can be done on the grid. Simics is an efficient, instrumented, system level instruction set simulator. It implements a lot of tools and provides the user with many capabilities as much as system simulation is concerned. In this thesis an inclusive presentation of Simics simulator is given.

This dissertation presents a series of studies that describe the impacts of, among other things, temperature and kinematics on inter-level dielectric (ILD) and metal chemical mechanical planarization (CMP) processes. The performance of CMP is often evaluated in terms of removal rate, uniformity, planarization length, step height, defects and resulting topography such as erosion and dishing. The assessment of these parameters is significantly dependent on the selection of tool and consumable set (polishing pad or slurry type), as well as the kinematics involved in the process. Variations in pressure, sliding velocity, temperature and slurry flow rate are just a few of the dynamic inputs that can affect polishing performance. The studies presented in this dissertation focus on some of these external parameters and how they influence the mechanisms involved with the CMP process and their overall outcome on performance.Studies presented in this dissertation include topics such as the effects wafer-ring configurations and wafer geometries on the applied wafer pressure distribution across a wafer surface. In addition to this, another study related to understanding applied wafer pressure investigated the estimation of the effective (envelop) pressure for patterned shallow trench isolation (STI) wafers during CMP. When considering the regularity of issues such as changing wafer geometries and wafer feature patterns, these two studies provided significant insight on the potential issues that could arise during CMP when dealing with such events, as well as potential solutions for controlling such events.Another study in this dissertation investigated the effects of polishing pad type on dielectric CMP performance. Polishing pads varied in thickness and grooving, and tests were done to characterize the tribological and thermal behavior of the pads under a wide range of p × V and slurry flow rate conditions. Of key importance in this study was observing any combined effects between changes in platen set point temperature and pad type on ILD removal rate.The greatest contribution to this dissertation involved studies related to the role of temperature in CMP. These studies implemented variable platen set point temperatures to further understand the thermal effects on parameters such as removal rate and coefficient of friction (COF). As a result of these studies, a new removal rate model based on flash heating was developed to describe observed non-linear trends in removal rate. The application of this model has shown great utility in removal rate prediction when compared to prior models.

This dissertation presents several studies relating to fundamental characterization of CMP consumables in planarization processes. These are also evaluated with the purposes of minimizing environmental impact and reducing cost of ownership (COO).The first study is conducted to obtain the retaining ring wear rate in a typical ILD CMP process and is specifically intended to investigate the effect of retaining ring materials and slot designs during the CMP process. The results show that retaining ring materials have effect on the COF, pad temperature and retaining ring wear rate, while retaining ring slot designs affect the pad surface abruptness. The second study is performed to compare the effect of different retaining ring slot designs on the slurry film thickness within the pad-wafer interface. A novel non-intrusive optical technique, dual emission UV-enhanced fluorescence (DEUVEF), was applied to accurately measure the film thickness of the slurry underneath the wafer during polishing. It is indicated that the optimized retaining ring slot design can significantly reduce the COO of CMP processes by increasing slurry utilization.A COF method is applied to measure the slurry mean residence time (MRT) during CMP. This technique uses transient COF data induced by a shift in slurry concentration to determine MRT. Variations in consumables as well as sliding velocity, pressure and slurry flow rate can affect the slurry MRT. One study in this dissertation focus on the effect of retaining ring slot designs on the slurry MRT. Another study compares the slurry MRT under same polishing conditions using pads with different groove width. Both studies are conducted on multiple sliding velocity, pressure and slurry flow rate variations to understand the characteristics of consumable designs. The method of measuring MRT during polishing presented in this dissertation can be easily applied in general CMP processes.The subsequent studies focus in the diamond conditioner discs characterization techniques. A newly developed method for determining active diamonds and aggressive diamonds on a diamond conditioner disc under a certain vertical load is elaborated in this dissertation. Later, this technique together with scanning electron microscopy (SEM) imaging is implemented to analyze diamond pullout and fracture in CMP. Five different types of diamond conditioner discs are subjected to a novel accelerated wear test respectively to compare the extent of diamond pullout and fracture under the same conditioning condition