Data Driven Design metodologija plačiai naudojama įvairiose programinėse sistemose. Šios metodologijos tikslas – atskirti bei lygiagretinti programuotojų ir projektuotojų veiklą. Sistemos branduolio funkcionalumas yra įgyvendinamas sąsajomis, o dinamika – scenarijų pagalba. Taip įvedamas abstrakcijos lygmuo, kurio dėka programinis produktas tampa lankstesnis, paprasčiau palaikomas ir tobulinamas, be to šiuos veiksmus galima atlikti lygiagrečiai. Darbo tikslas buvo sukurti automatinį kodo generatorių, kuris transformuotų grafiškai sumodeliuotą scenarijų į programinį kodą. Generuojant programinį kodą automatiškai ženkliai sumažėja sintaksinių bei loginių klaidų tikimybė, viskas priklauso nuo sumodeliuoto scenarijaus. Kodas sugeneruojamas labai greitai ir visiškai nereikalingas programuotojo įsikišimas. Šis tikslas pasiektas iškėlus biznio logikos projektavimą į scenarijaus projektavimą, o kodo generavimo posistemę realizavus žiniatinklio paslaugos principu. Kodas generuojamas neprisirišant prie konkrečios architektūros, technologijos ar taikymo srities panaudojant įskiepių sistemą . Grafiniame scenarijų kūrimo įrankyje sumodeliuojamas scenarijus ir tada transformuojamas į metakalbą , iš kurios ir generuojamas galutinis programinis kodas. Metakalba – tam tikromis taisyklėmis apibrėžta „XML “ kalba. Realizavus eksperimentinę sistemą su didelėmis problemomis nebuvo susidurta. Naujos sistemos modeliavimas projektavimo įrankiu paspartino kūrimo procesą septynis kartus. Tai įrodo... [toliau žr. visą tekstą] / Data Driven Design methodology is widely used in various program systems. This methodology aim is to distinguish and parallel software developer and scenario designer’s work. Core functionality is implemented via interfaces and dynamics via scenario support. This introduces a level of abstraction, which makes software product more flexible easily maintained and improved, in addition these actions can be performed in parallel. The main aim of this work was to create automatic code generator that transforms graphically modeled scenario to software code. Automatically generated software code restricts probability of syntactic and logical errors, all depends on scenario modeling. Code is generated instantly and no need software developer interference. This aim is achieved by moving business logic designing to scenario designing process and code generator service making as a “Web service”. Using cartridge based system code is generated not attached to a specific architecture, technology or application domain. In graphical scenario modeling tool scenario is modeled and transformed to metalanguage, from which software code is generated. Metalanguage – with specific rules defined “XML” language. Experimental system was developed with no major problems. New project modeling with our modeling tool speeded the development process by seven times. This proves modeling tool advantage over manual programming.

Nous nous intéressons au développement prouvé de composants formels pour un générateur de code pré-qualifié. Ce dernier produit un code séquentiel (C et Ada) pour des modèles d'entrée qui combinent les flots de données et de contrôle et qui présentent des possibilités d'exécution concurrente (Simulink/Stateflow et Scicos). Le développement prouvé permet de réduire le coût des tests et d'augmenter l'assurance des outils développés avec cette approche vis-à-vis de la qualification. Les phases de spécification, de développement et de vérification des outils développés sont effectuées avec l'assistant de preuve Coq. Ce dernier permet d'extraire le contenu calculatoire des composants en préservant les propriétés prouvées en Coq. Ce code extrait est ensuite intégré dans une chaîne complète de développement (chaîne de GeneAuto). Nous présentons un cadre formel, inspiré de l'analyse statique, qui s'appuie sur la sémantique abstraite et qui est instanciable sur plusieurs composants du générateur de code. Nous nous basons sur les ensembles partiellement ordonnés et sur le calcul de point fixe pour définir le cadre et effectuer les différentes analyses des composants du générateur de code. Ce cadre formel comporte toutes les preuves communes aux composants et indépendantes des analyses effectuées. Deux composants sont étudiés : l'ordonnanceur et le typeur des modèles d'entrée. / We are interested in the proved development of formal components for a pre-qualified code generator. This produces a sequential code (C and Ada) for input models that combine data and control flows, with potential concurrent execution (Simulink/Stateflow and Scicos). The proved development reduces test cost and increases insurance of components developed with this approach regarding the qualification. Phases of specification, development and verification of the developed components are done with the Coq proof assistant. This allows to extract the computational content of the components preserving the properties proved in Coq. The extracted code is then integrated into the complete development tool-chain (GeneAuto tool-chain). We present a formal framework, inspired from static analysis, based on the abstract semantics which is instantiable to several components of the code generator. We rely on partially ordered sets and fixed-point to define de formal framework and to perform the various analysis of components of the code generator. This formal framework includes all proofs common to the components and independent from the performed analyses. Two components are studied : the scheduler and the type checker of input models.

As the backbone of many computing environments today, it is important that process virtual machines be both performant and robust in mobile, personal desktop, and enterprise applications. This thesis focusses on code generation within these virtual machines, particularly addressing situations where redundant work is being performed. The goal is to exploit information sharing in order to improve the performance and robustness of virtual machines that are accelerated by native code generation. First, the thesis investigates the potential to share generated code between multiple threads in a dynamic binary translator used to perform instruction set simulation. This is done through a code generation design that allows native code to be executed by any simulated core and adding a mechanism to share native code regions between threads. This is shown to improve the average performance of multi-threaded benchmarks by 1.4x when simulating 128 cores on a quad-core host machine. Secondly, the ahead-of-time code generation system used for executing Android applications is improved through the use of profiling. The thesis investigates the potential for profiles produced by individual users of applications to be shared and merged together to produce a generic profile that still provides a lot of benefit for a new user who is then able to skip the expensive profiling phase. These profiles can not only be used for selective compilation to reduce code-size and installation time, but can also be used for focussed optimisation on vital code regions of an application in order to improve overall performance. With selective compilation applied to a set of popular Android applications, code-size can be reduced by 49.9% on average, while installation time can be reduced by 31.8%, with only an average 8.5% increase in the amount of sequential runtime required to execute the collected profiles. The thesis also shows that, among the tested users, the use of a crowd-sourced and merged profile does not significantly affect their estimated performance loss from selective compilation (0.90x-0.92x) in comparison to when they they perform selective compilation with their own unique profile (0.93x). Furthermore, by proposing a new, more powerful code generator for Android’s virtual machine, these same profiles can be used to perform focussed optimisation, which preliminary results show to increase runtime performance across a set of common Android benchmarks by 1.46x-10.83x. Finally, in such a situation where a new code generator is being added to a virtual machine, it is also important to test the code generator for correctness and robustness. The methods of execution of a virtual machine, such as interpreters and code generators, must share a set of semantics about how programs must be executed, and this can be exploited in order to improve testing. This is done through the application of domain-aware binary fuzzing and differential testing within Android’s virtual machine. The thesis highlights a series of actual code generation and verification bugs that were found in Android’s virtual machine using this testing methodology, as well as comparing the proposed approach to other state-of-the-art fuzzing techniques.

In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.

The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level descriptions to aid code selection and storage allocation. The view taken in the thesis is that a description specializes a framework with a particular architecture. Independently, the framework must support other translation algorithms without constraining their freedom or forcing them towards architecture-specific idioms. The first contribution is an architectural description language with features tuned towards better parameterizability. Emphasis is laid on addressing site (compile time) parameterizability. Within the notation, the type system of the machine is decoupled from that of the language with the mapping being left to the user as a compile-time parameterization. This gives one more degree of freedom for the user to decide on the precision required based on the available realizations. We also give adequate representation to addressing modes. They are considered to be almost equivalent to operations in complexity. This makes the specification simpler for operations. From the framework's perspective, as a second contribution, we propose an algorithm for maintaining registers during allocation. Register allocation algorithms depend on the framework to inform them when registers are exhausted. In such a situation, we pro- pose an adaptation of bipartite graph matching to keep track of register usage during translation in the presence of architec- tural constraints. The research also aims at structuring both the specification and software to prevent the closed-syntax bottle- neck of a lot of specification languages. We also describe the architecture of the implementation in terms of a very flexible model called the blackboard model.

<p>In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards. </p><p>This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates. </p><p>The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well. </p><p>The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.</p>

There exists a vast literature on nonuniform random variate generators. Most of these generators are especially designed for a particular distribution. However in pratice only a few of these are available to practioners. Moreover for problems as (e.g.) sampling from the truncated normal distribution or sampling from fairly uncommon distributions there are often no algorithms available. In the last decade so called universal methods have been developed for these cases. The resulting algorithms are fast and have properties that make them attractive even for standard distributions. In this contribution we describe the concept of Automatic random variate generation where these methods are used to produce a single piece of code in a high level programming language. Using a web-based front-end to such a program this is an easy-to-use source for researchers and programmers for high quality generators for a large class of distributions. Using our UNURAN library we have implemented such a system, which is accessable at <a href="http://statistik.wu-wien.ac.at/anuran" target="_blank">http://statistik.wu-wien.ac.at/anuran</a>. / Series: Preprint Series / Department of Applied Statistics and Data Processing

Eine wichtige Aufgabe bei der Softwareentwicklung ist das Auffinden von Fehlern und das Verstehen ihrer Ursachen. Zur Unterstützung dieser Aufgabe gibt es zahlreiche De-bugger. Bei der Nutzung von Softwaregeneratoren benötigt man zum Debuggen spezielle Informationen. In dieser Arbeit werden Anforderungen an einen Debugger für Software-generatoren definiert. Dazu werden zunächst strukturell ähnliche Softwaregeneratoren auf ihre Debugger untersucht und grundsätzliche Debuggertypen identifiziert. Aus diesen werden 15 Anforderungen formuliert, die der hier beispielhaft betrachtete Softwaregener-ator erfüllen soll. Anschließend erfolgen eine Verallgemeinerung der Ergebnisse und eine kurze Diskussion der Umsetzung auf der Plattform JetBrains MPS.

This thesis deals with description of CRC codes, which is a type of polynomial error correction codes, and description of CAN and CAN FD protocols used in automobiles for data transmission between sensors. One of the security elements is usage of the CRC codes with the Hamming distance 6. Unfortunately, both protocols contain a design vulnerability which causes that some received messages with one wrong bit do not have to be detected by the protocol. The aim of the thesis was to describe this vulnerability and found out, if it was possible to eliminate it by using different CRC code. It managed to characterize all messages, which are not during this vulnerability detected by CRC code and based on that it was possible to prove, that the probability of error does not depend on a CRC code choice of a fixed length. 1

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