This work deals with interfering signals and noises, possibilities of their measurement, their reduction and afterwards with design of LISN. The theoretical part analyzes formation of interfering signals, their types, with possible measuring instruments for each type of these signals and their properties. In framework of practical part LISN for long-term load of 5A, frequency range from 150 kHz to 30 MHz, with possibility to measure symmetrical and asymmetrical noise separately and also with possibility to switch to normal mode of LISN was developed. For better results LISN was realized as two stage LC filter.

This thesis deals with voltage disturbances in audio-frequency propagated in distribution networks. In the theoretical part, a creation and effect of these interferences are discussed as well as current methods of their measurement. In the practical part of the thesis, a measurement device based on a frequency filter was developed. This measurement device is able to measure audio-frequency disturbances up to 250kHz without suppresion of audio-frequency disturbances. The maximum frequency on the output is limited by either 125kHz or 250 kHz filter.

With the development of power electronics, electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues have become more and more important for both power converter designers and customers. This dissertation studies EMI noise emission characterization and modeling in power converters. A modular-terminal-behavioral (MTB) equivalent EMI noise source modeling approach is proposed. This work is the first to systematically develop a 3-terminal EMI noise source model for a switching phase-leg device module. Each module is modeled as pairs of equivalent noise current sources and source impedances. Although the proposed MTB modeling approach applies the linear circuit theory to a semiconductor switching device, which exhibits nonlinear behavior during switching transients, the analysis and experiments show that the nonlinearity has negligible practical effect on the modeling methodology. The validation range of the modeling methodology has been analyzed. One of the differences between the proposed MTB model and the other state-of-the-art models is that the MTB model characterizes and predicts the CM and DM noise simultaneously. The inseparable high-frequency CM and DM noise characteristics contributed by the source impedance and propagation path are analyzed. A comprehensive evaluation of different EMI noise source modeling approaches according to the criteria of accuracy, feasibility and generality has been presented. Results show that the MTB modeling approach is more accurate, feasible and general than other approaches. The modular and terminal characteristics of the MTB noise source model are verified in two more complicated cases. One example is the application of the MTB equivalent source model in a half-bridge AC converter with variable switching conditions. Although the MTB model is derived under a certain operating condition, the models under different conditions can be combined together to predict the EMI noise for the converter with variable switching conditions. Another example is the application of the MTB equivalent source model in multi-phase-leg converters. The EMI noise of a full-bridge converter is predicted based on the MTB equivalent source model of one phase-leg module. The implementation procedures and results for both applications are verified by the experiment. The applicability of the MTB model in different type of converters is discussed. Based on the MTB model, EMI noise management is explored. The parametric study based on the MTB model is demonstrated by selecting DC-link decoupling capacitors for voltage source converter (VSC). The EMI effect of a decoupling capacitor for a device s safe operation is analyzed, and this analysis shows the terminal characteristics of the MTB model. Both the EMI and voltage overshoot are predicted by the MTB model. A completed converter-level EMI model can be derived based on the noise source model and propagation path model. This model makes it possible to optimize the EMI filter design and study the EMI noise interactions between converters in a power conversion system. / Ph. D.

This dissertation studies modeling and control issues of parallel three-phase pulse-width modulated (PWM) converters. The converters include three-phase boost rectifiers, voltage source inverters, buck rectifiers and current source inverters. The averaging of the parallel converters is performed based on a generic functional switching unit, which is called a phase leg in boost rectifiers and voltage source inverters, and a rail arm in buck rectifiers and current source inverters. Based on phase-leg and rail-arm averaging, the developed models are not only equivalent to the conventional three-phase converter models that are based on phase-to-phase averaging, but they also preserve common-mode information, which is critical in the analysis of the parallel converters. The models reveal such parallel dynamics as reactive power circulation and small-signal interaction. A unique feature of the parallel three-phase converters is a zero-sequence circulating current. This work proposes a novel zero-sequence control concept that uses variable zero-vectors in the space-vector modulation (SVM) of the converters. The control can be implemented within an individual converter and is independent from the other control loops for the converter. Therefore, it greatly facilitates the design and expansion of a parallel system. Proper operation of the parallel converters requires an explicit load-sharing mechanism. In order to have a modular design, a droop method is recommended. Traditionally, however, a droop method has to compromise between voltage regulation and load sharing. After parametric analysis, a novel droop method using a gain-scheduling technique is proposed. The numeric analysis shows that the proposed droop method can achieve both good voltage regulation and good load sharing. An interleaving technique is often used in parallel converter systems in order to reduce current ripples. Because of its symmetrical circuit structure, the parallel three-phase converter system can reduce both differential-mode and common-mode noise with a center-aligned symmetrical SVM. Based on the concept that a symmetrical circuit can reduce common-mode dv/dt noise, a conventional three-phase, four-leg inverter is modified so that its fourth leg is symmetrical to the other three legs. The common-mode dv/dt noise can be practically eliminated with a new modulation strategy. Meanwhile, with a modified control design, the new four-leg inverter still can handle low-frequency common-mode components that occur due to unbalanced and nonlinear load. / Ph. D.

In this work, a modeling approach is delineated and described in detail; predominantly done in the time domain from low frequency, DC, to high frequencies, 100 MHz. Commercially available computer aided design tools will be used to determine the propagation path in a given structure. Next, an integrated transmission-line filter — fabricated using planar processing technologies — is modeled to accurately predict the EMI characteristics of the system. A method was derived to model the filter's performance in the time-domain while accurately depicting the highly frequency dependant transmission-line properties. A system model of a power factor correction (PFC) boost converter was completed by using active device models for diodes, MOSFETs, and the gate driver. In addition, equivalent circuits were used to characterize high frequency impedances of the passive components. A PFC boost converter was built and used to validate the model. The PFC operated at a peak output power of 1 kW, switching at 400 kHz, with a universal input ranging from 90-270 VRMS with unity power factor. The time-domain and EMI frequency spectrum waveforms are experimentally measured and agree very well with the simulated values; within 5 dB for EMI. The transmission-line filter was also manufactured for model verification, and it is tested for the first time with an operating converter: a PFC at 50 W output and 50 VDC input. The small signal characteristics match the model very well. In addition, impedance interactions between the filter, the converter, and the EMI measurement set-up are discussed, evaluated, measured, and improved to minimize undesired resonances and increase low-frequency EMI attenuation. Experimentally measured attenuation provided by the filter in the range from 100 kHz to 100 MHz was 20-50 dBμV. The simulation also shows a similar attenuation, with the exception of one key resonance not seen in the simulation. / Master of Science

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.

This dissertation is aimed at the development of a current mode instrumentation amplifier (CMIA) with a high common mode input range. This characteristic is obtained due to the rail-to-rail operational amplifiers (opamps). These opamps are built with rail-to-rail differential amplifiers as input stages, and with cascode-based output stages, which are able to copy its current by adding identical branches and connecting their gates without the voltage degradation as the known CMIA topologies. The main contribution of this work is the development of a rail-to-rail current mode instrumentation amplifier, analyzing the pros and cons of this topology. The functionality of the proposed topology is shown through measured results of a manufactured integrated circuit. This first prototype, although it was operated in a large input common mode range, presented insufficient values of CMRR (Common Mode Rejection Ratio) and VOS (Offset voltage). These two characteristics were studied and modeled, the instrumentation amplifier was re-designed, and simulated results demonstrate important improvements. / Esta dissertação tem como objetivo o desenvolvimento de um amplificador de instrumentação em modo corrente com uma ampla faixa de entrada em modo comum. Esta característica é obtida graças ao emprego de estágios de amplificação rail-to-rail na entrada e a geração do sinal de saída através do espelhamento da corrente diretamente dos gates dos transistores do estágio ao invés da alternativa clássica, onde espelhos são ligados em série e degradam a excursão do sinal de saída. Com esta proposta, é possível a implementação de ampops com entrada e saída rail-to-rail. A principal contribuição deste trabalho é analisar as vantagens e desvantagens da utilização destas soluções na implementação de um amplificador de instrumentação com entrada rail-to-rail. A funcionalidade da topologia proposta é demonstrada através dos resultados medidos de um circuito integrado fabricado. Este primeiro protótipo, apesar do bom funcionamento em toda a faixa de entrada em modo comum, apresentou valores insatisfatórios de CMRR (Common Mode Rejection Ratio) e de VOS (Tensão de offset), o que levou a um aprofundamento no estudo e modelagem destas características. A partir disto, o circuito foi re-projetado e os resultados de simulação demonstram melhorias bastante significativas em suas características.

Actuellement, le développement de semiconducteurs et la demande croissante de convertisseurs en électronique de puissance dans les différents domaines de l’énergie électrique, notamment pour des applications dans l’aéronautique et les réseaux de transport et de distribution, imposent de nouvelles spécifications comme le fonctionnement à hautes fréquences de commutation, densités de puissance élevées, hautes températures et hauts rendements. Tout ceci contribue au fort développement des composants en SiC (Carbure de Silicium). Cependant, ces composants créent de nouvelles contraintes en Compatibilité Electromagnétique (CEM) à cause des conditions de haute fréquence de commutation et fortes vitesses de commutation (forts di/dt et dv/dt) en comparaison à d’autres composants conventionnels de l'électronique de puissance. Une étude des perturbations générées par les composants SiC est donc nécessaire. L'objectif de ce travail est de donner aux ingénieurs amenés à concevoir des convertisseurs une méthode capable de prédire les niveaux d'émissions conduites générées par un convertisseur électronique de puissance qui intègre des composants en SiC. La nouveauté du travail présenté dans cette thèse est l’intégration de différents modèles de type circuit pour tous les constituants d’un convertisseur (un hacheur série est pris comme exemple). Le modèle est valable pour une gamme de fréquences de 40Hz à 30MHz. Des approches de modélisation des parties passives du convertisseur sont présentées. Ces approches sont différentes selon que les composants modélisés soient disponibles ou à concevoir : elles sont basées sur des mesures pour la charge et les capacités ; elles sont basées sur des simulations prédictives pour routage du convertisseur. Le modèle complet du convertisseur (éléments passifs et actifs) est utilisé en simulation pour prédire les émissions conduites reçues dans le réseau stabilisateur d’impédance de ligne. Le modèle est capable de prédire l'impact de différents paramètres comme le routage, les paramètres de contrôle comme les différents rapports cycliques et les résistances de grille avec des résultats satisfaisants dans les domaines temporels et fréquentiels. Les résultats obtenus montrent que le modèle peut prédire les perturbations en mode conduit pour les différents cas jusqu'à une fréquence de 15MHz. Finalement, une étude paramétrique du convertisseur a été élaborée. Cette étude a permis de voir l’influence de la qualité des différents modèles comme les éléments parasites du routage, des composants passifs et actifs et d'identifier les éléments qui ont besoin d’un modèle précis pour avoir des résultats valides dans la prédiction des perturbations conduites. / The recent technological progress of semiconductors and increasing demand for power electronic converters in the different domains of electric energy particularly for applications in aeronautics and networks of transport and distribution impose new specifications such as high frequencies, high voltages, high temperatures and high current densities. All of this contributes in the strong development of SiC (Silicon Carbide) components. However these components create new issues in Electromagnetic Compatibility (EMC) because of the conditions of high frequency switching and high commutation speeds (high di/dt and dv/dt) compared to other conventional components in power electronics. A precise study of the emissions generated by SiC components is therefore necessary. The aim of this work is to give a method able to predict levels of conducted emissions generated by a power electronics converter with SiC components to engineers which design power converters. The novelty of the work presented in this thesis is the integration of different modeling approaches to form a circuit model of a SiC-based converter (a buck dc–dc converter is considered as an example). The modeling approach is validated in the frequency range from 40Hz to 30MHz. Modeling approaches of the passive parts of the converter are presented. Theses approaches differs according to whether the component is existing or to be designed : they are based on measurements for the load and capacitors; they are based on numerical computation and analytical formulations for PCB. The complete model obtained (passive and active components) is used in simulations to predict the conducted emissions received by the line impedance stabilization network. The model is able to predict the impact of various parameters such as PCB routing, the control parameters like duty cycles and different gate resistors in the time and frequency domains. A good agreement is obtained in all cases up to a frequency of 15MHz. Finally, a parametric study of the converter has been elaborated. This study allowed to see the influence of different models such as parasitic elements of the PCB, passive and active components and to identify the elements that need a precise model to obtain valid results in the prediction of conducted EMI.

L’intégration de l’électronique dans des environnements sévères d’un point de vue électromagnétique a entraîné en contrepartie l’apparition de problèmes de compatibilité électromagnétique (CEM) entre les différents systèmes. Afin d’atteindre un niveau de performance satisfaisant, des tests de sécurité et de certification sont nécessaires. Ces travaux de thèse, réalisés dans le cadre du projet SIMUCEDO (SIMUlation CEM basée sur la norme DO-160), contribuent à la modélisation du test de qualification "Bulk Current Injection" (BCI). Ce test, abordé dans la section 20 dans la norme DO-160 dédiée à l’aéronautique, est désormais obligatoire pour une très grande gamme d’équipements aéronautiques. Parmi les essais de qualification, le test BCI est l’un des plus contraignants et consommateurs du temps. Sa modélisation assure un gain de temps, et une meilleure maîtrise des paramètres qui influencent le passage des tests CEM. La modélisation du test a été décomposée en deux parties : l’équipement sous test (EST) d’une part, et la pince d’injection avec les câbles d’autre part. Dans cette thèse, seul l’EST est pris en compte. Une modélisation "boîte grise" a été proposée en associant un modèle "boîte noire" avec un modèle "extensif". Le modèle boîte noire s’appuie sur la mesure des impédances standards. Son identification se fait avec un modèle en pi. Le modèle extensif permet d’étudier plusieurs configurations de l’EST en ajustant les paramètres physiques. L’assemblage des deux modèles en un modèle boîte grise a été validé sur un convertisseur analogique-numérique (CAN). Une autre approche dénommée approche modale en fonction du mode commun (MC) et du mode différentiel (MD) a été proposée. Elle se base sur les impédances modales du système sous test. Des PCB spécifiques ont été conçus pour valider les équations développées. Une investigation est menée pour définir rigoureusement les impédances modales. Nous avons démontré qu’il y a une divergence entre deux définitions de l’impédance de MC dans la littérature. Ainsi, la conversion de mode (ou rapport Longitudinal Conversion Loss : LCL) a été quantifiée grâce à ces équations. Pour finir, le modèle a été étendu à N-entrées pour représenter un EST de complexité industrielle. Le modèle de l’EST est ensuite associé avec celui de la pince et des câbles travaux réalisés au G2ELAB. Des mesures expérimentales ont été faites pour valider le modèle complet. D’après ces mesures, le courant de MC est impacté par la mise en œuvre des câbles ainsi que celle de l’EST. Il a été montré que la connexion du blindage au plan de masse est le paramètre le plus impactant sur la distribution du courant de MC. / Electronic equipments intended to be integrated in aircrafts are subjected to normative requirements. EMC (Electromagnetic Compatibility) qualification tests became one of the mandatory requirements. This PhD thesis, carried out within the framework of the SIMUCEDO project (SIMulation CEM based on the DO-160 standard), contributes to the modeling of the Bulk Current Injection (BCI) qualification test. Concept, detailed in section 20 in the DO-160 standard, is to generate a noise current via cables using probe injection, then monitor EUT satisfactorily during test. Among the qualification tests, the BCI test is one of the most constraining and time consuming. Thus, its modeling ensures a saving of time, and a better control of the parameters which influence the success of the equipment under test. The modeling of the test was split in two parts : the equipment under test (EUT) on one hand, and the injection probe with the cables on the other hand. This thesis focuses on the EUT modeling. A "gray box" modeling was proposed by associating the "black box" model with the "extensive" model. The gray box is based on the measurement of standard impedances. Its identification is done with a "pi" model. The model, having the advantage of taking into account several configurations of the EUT, has been validated on an analog to digital converter (ADC). Another approach called modal, in function of common mode and differential mode, has been proposed. It takes into account the mode conversion when the EUT is asymmetrical. Specific PCBs were designed to validate the developed equations. An investigation was carried out to rigorously define the modal impedances, in particular the common mode (CM) impedance. We have shown that there is a discrepancy between two definitions of CM impedance in the literature. Furthermore, the mode conversion ratio (or the Longitudinal Conversion Loss : LCL) was quantified using analytical equations based on the modal approach. An N-input model has been extended to include industrial complexity. The EUT model is combined with the clamp and the cables model (made by the G2ELAB laboratory). Experimental measurements have been made to validate the combined model. According to these measurements, the CM current is influenced by the setup of the cables as well as the EUT. It has been shown that the connection of the shield to the ground plane is the most influent parameter on the CM current distribution.

The Archimedean spiral antenna is well-known for its broadband characteristics with circular polarization and has been investigated for several decades. Since their development in the late 1950's, establishing an analytical expression for the characteristics of spiral antenna has remained somewhat elusive. This has been studied qualitatively and evaluated using numerical and experimental techniques with some success, but many of these methods are not convenient in the design process since they do not impart any physical insight into the effect each design parameter has on the overall operation of the spiral antenna. This work examines the operation of spiral antennas and obtains a closed-form analytical solution by conformal mapping and transmission line model with high precision in a wide frequency band. Based on the analysis of spiral antenna, we propose two novel design processes for the stripline-fed Archimedean spiral antenna. This includes a stripline feed network integrated into one of the spiral arms and a broadband tapered impedance transformer that is conformal to the spiral topology for impedance matching the nominally-high input impedance of the spiral. A Dyson-style balun located at the center facilitates the transition between guided stripline and radiating spiral modes. Measured and simulated results for a probe-fed design operating from 2 GHz to over 20 GHz are in excellent agreements to illustrate the synthesis and performance of a demonstration antenna. The research in this work also provides the possibility to achieve conformal integration and planar structural multi-functionality for an Unmanned Air Vehicle (UAV) with band coverage across HF, UHF, and VHF. The proposed conformal mapping analysis can also be applied on periodic coplanar waveguides for integrated circuit applications.