A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures. / Dissertation (MEng)--University of Pretoria, 2012. / Electrical, Electronic and Computer Engineering / unrestricted

Ce travail porte sur la conception, la fabrication et la caractérisation d’une photodiode très haut débit (UTC PD) et son intégration avec un préamplificateur optique à semi-conducteur (SOA) pour les liaisons optiques à courte distance à 100 Gbit/s en bandes C et O. Il porte également sur la conception d'un duplexeur (Tx / Rx) avec liaison montante en bande C et liaison descendante en bande O. L'intégration monolithique d’un SOA avec une photodiode haut débit sans filtre optique entre les deux présente des avantages majeurs parmi lesquels: - Augmentation de la distance de transmission. - Augmentation du nombre d'utilisateurs connectés. - Diminution des coûts globaux de fabrication incluant l’assemblage. La première partie de cette étude porte sur l'optimisation SOA pour un fonctionnement à forte puissance (Psat). Un faible facteur de bruit (NF) et une faible dépendance à la polarisation (PDL) sont requis pour les récepteurs préamplifiés. De plus, un fonctionnement du et opérer en régime linéaire est nécessaire pour les schémas de modulation complexes. Le SOA actuel possède un gain de 18 dB avec un facteur de bruit de 8 dB, une faible PDL (<2 dB), et une bonne puissance de saturation en entrée (-8 dBm). Grâce à l’optimisation de la structure verticale du SOA et de son couplage avec la fibre les performances attendues sont améliores : Psat >-5 dBm, NF <8 dB, PDL et gain similaire. D'autre part, les interconnexions électriques de la photodiode ont été optimisées ce qui a permis de démontrer des photodiodes avec une bande passante supérieure à 100 GHz. Les photodiodes présentent un fort coefficient de réponse (R) (0,6 A/W à 1,3 μm et 0,55 A/W à 1,55 μm) et une faible PDL <1 dB. Un fort courant de saturation de 14 mA à 100 GHz a aussi été démonté. Enfin, la caractérisation des SOA-UTC réalisés a montré simultanément une très forte responsivité (95 A/W), une faible dépendance à la polarisation PDL (<2 dB), un faible NF (8 dB) et une large bande passante à 3 dB (> 95 GHz), qui placent nos composants au meilleur niveau de l’état de l’art avec un produit gain-bande record de 6,1 THz. Les Mesures numériques à 64 Gbit/s montrent que notre récepteur atteint une sensibilité de -17 dBm pour un taux d'erreur de 10-9, et la sensibilité attendue à 100 Gbit/s est de -14 dBm / This work focuses on the design, fabrication and measurements of a uni-travelling carrier high speed photodiode (UTC PD) and its integration with a semiconductor optical preamplifier (SOA) for short reach 100 Gbit/s optical links, in O- and C- bands. This work also focuses on the design of a duplexer (Tx/Rx) with downstream in O-band and upstream in C-band. The SOA monolithic integration with a high speed PD without an optical filter in between yields major benefits among which: - Increase in the transmission distance. - Increase in the split ratio correlated to the number of connected users. - Decrease of the overall fabrication and assembling cost. The first part of this work is dedicated to optimizing the SOA for high power operation (Psat). The low noise figure (NF), and polarization dependence loss (PDL) are critical parameters for a preamplified receiver. Also complex modulation formats require linear gain regime of the SOA. The current SOA presents 18 dB gain with NF (8 dB), low PDL (<2 dB), and good input power saturation (-8 dBm). Thanks to further optimization of the SOA vertical structure and coupling with the optical fiber, the expected SOA performance is higher Psat >-5 dBm, NF <8 dB, similar PDL and gain. Secondly, the electrical interconnects of the photodiode is optimized to increase the photodiodes’ bandwidth, which allows to demonstrate photodiode with >100 GHz bandwidth. The PD presents high responsivity (R) (0,6 A/W at 1,3 μm and 0.55 A/W at 1,55 μm) and low PDL <1 dB. Also the saturation photocurrent is high (14 mA at 100 GHz). Finally, the SOA-UTC demonstrates high responsivity (95 A/W), low PDL (<2 dB), low NF (8 dB) and a wide 3 dB bandwidth (>95 GHz), which yields a record gain-bandwidth product of 6.1 THz. Large signal measurements at 64 Gbit/s show that our receiver reaches a low sensitivity of -17 dBm for a bit error rate of 10-9, and is expected to reach -14 dBm at 100 Gbit/s

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