Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.

Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.:1. Introduction and Motivation 10 2. Organic Semiconductors and Thin-Film Transistors 12 2.1. Fundamentals of Organic Semiconductors 12 2.1.1. Structural and Electronic Properties 12 2.1.2. Polarons and Trap States 15 2.1.3. Doping of Organic Semiconductors 16 2.2. Charge-Carrier Transport in Organic Semiconductors 18 2.2.1. Field-Effect Mobility 18 2.2.2. Gaussian Disorder Model 21 2.2.3. Variable-Range Hopping Models 24 2.2.4. Fishchuk Model 26 2.3. Organic Field-Effect Transistors 27 2.3.1. Transistor Geometry 27 2.3.2. Transistor Equations 29 2.3.3. Evaluation of Mobility 32 2.3.4. Threshold Voltage 34 2.3.5. Contact Resistance 35 2.3.6. Au-SAMs 38 2.3.7. Dielectric 39 2.3.8. Scaling and Short Channel Effects 41 2.3.9. Stability and Bias-Stress 43 2.4. Device Simulation 44 3. Materials and Methods 46 3.1. Materials 46 3.2. Sample Preparation 50 3.2.1. Sample Preparation in cooperation with the industrial partner 51 3.2.2. Sample Preparation at IAPP 52 3.2.3. Staggered Transistors at IAPP 56 3.3. Sample Characterization 57 3.3.1. Electrical Measurement Setup 57 3.3.2. Parameter Extraction 60 3.3.3. Contact Resistance 61 3.3.4. Kelvin-Probe Atomic Force Microscopy 64 3.3.5. UPS Measurement 65 4. Organic Field-Effect Transistors - Experiment and Simulation 67 4.1. Bottom-Gate Transistors 67 4.1.1. Semiconductors 67 4.1.2. Bipolar Transport 72 4.1.3. Electrode Treatments 74 4.1.4. Channel Treatments 77 4.1.5. Polymer Transistors 79 4.2. Polymer Transistors at Room Temperature 85 4.2.1. Parameter Extraction 85 4.2.2. Four-Point-Probe Measurements 90 4.2.3. Transferline Methode 96 4.2.4. UPS Measurements 100 4.3. Cryostat Measurements 102 4.3.1. Transistor Characteristics 102 4.3.2. Contact Resistance 105 4.3.3. Density of States 107 4.4. Transistor Simulation 110 4.4.1. Introduction of Device Simulation with Genius 110 4.4.2. Mesh and Geometry 111 4.4.3. Contact Resistance of Charge-Carrier Injection 112 4.4.4. Temperature Dependent Simulations 114 4.4.5. Implementation of Donor Traps 116 4.4.6. Poole-Frenkel Discussion 118 4.4.7. Contact Resistance of Geometry 122 4.4.8. Simulation with Advanced Mobility Models 123 4.5. Bias-Stress Reliability 128 4.5.1. Bias-Stress Phenomena 128 4.5.2. Doped Transistors 136 4.5.3. Polymer Transistors 145 5. Conclusion and Outlook 150 A. Appendix 154 A.1. Charge-Carrier Mobility measurements for solar cell materials 154 A.2. Simulation pictures 154 B. Bibliography 160

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

The high-frequency and low-voltage operation of organic thin-film transistors (OTFTs) is a key requirement for the commercial success of flexible electronics. Significant progress has been achieved in this regard by several research groups highlighting the potential of OTFTs to operate at several tens or even above 100 MHz. However, technology maturity, including scalability, integrability, and device reliability, is another crucial point for the semiconductor industry to bring OTFT-based flexible electronics into mass production. These requirements are often not met by high-frequency OTFTs reported in the literature as unconventional processes, such as shadow-mask patterning or alignment with unrealistic tolerances for production, are used. Here, ultra-short channel vertical organic field-effect transistors (VOFETs) with a unity current gain cut-off frequency (fT) up to 43.2 MHz (or 4.4 MHz V−1) operating below 10 V are shown. Using state-of-the-art manufacturing techniques such as photolithography with reliable fabrication procedures, the integration of such devices down to the size of only 12 × 6 μm2 is shown, which is important for the adaption of this technology in high-density circuits (e.g., display driving). The intrinsic channel transconductance is analyzed and demonstrates that the frequencies up to 430 MHz can be reached if the parasitic electrode overlap is minimized.