Ce sujet s'inscrit dans la continuité des travaux commencés au sein du L2ES dans le cadre du programme ECCE en partenariat avec CREEBEL qui assure le nancement. La plateforme ECCE est un véhicule hybride électrique série à 4 roues indépendantes d'une puissance nominale en propulsion de 120kW électrique. La source d'énergie principale est constituée de deux moteurs diesels entraînant deux alternateurs. L'énergie électrique produite alimente les 4 moteurs électriques de traction et le reste est stocké dans le pack des batteries. Cette thèse développe les stratégies de couplage énergétique entre ce pack des batteries et les supercondensateurs an d'assurer au véhicule une dynamique de fourniture et du stockage de l'énergie électrique. Une étude bibliographique a permis de passer en revue le bilan technologique et les applications potentielles des supercondensateurs, puis d'élaborer le modèle simplié des supercondensateurs qui traduit dèlement le comportement des cellules durant les phases de charge et de décharge. Diérentes topologies des convertisseurs DC/DC avec des stratégies originales de gestion d'énergie électrique embarquée sont traitées. Les topologies proposées sont basées sur les convertisseurs Buck-Boost et les convertisseurs DC/AC-AC/DC à étage intermédiaire haute fréquence. Pour une raison de coût, les maquettes expérimentales des topologies ont été réalisées à l'échelle réduite ( 1/10 ). Les résultats expérimentaux obtenus ont permis de comparer les performances des topologies pour deux types de commande. La stratégie de gestion d'énergie à base des correcteurs polynomiaux (RST) est comparée à celle utilisant des correcteurs PI classiques. Ces études comparatives ont permis de choisir la meilleure topologie destinée au couplage des supercondensateurs sur le bus continu du banc ECCE.

<p>Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. </p><p>This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.</p>

This thesis presents a distributed power-management architecture for concentrating photovoltaic (CPV) systems. Specifically, the Δ-conversion scheme with voltage equalization is analyzed and verified for the CPV system from Morgan Solar, Inc. This architecture uses inverting buck-boost converters, denoted Δ-converters, which equalize the voltages of neighbouring CPV cells in a series-connected string of cells and improve the systems tolerance to parameter variations. The power benefits of Δ-conversion and the Δ-converter current distributions are investigated using statistical simulations. The effectiveness of Δ-conversion in the presence of randomly distributed mismatches is demonstrated, and current cascading is identified as the main design challenge. The Δ-converter is modelled and compensated using Middlebrook's Extra Element Theorem. Analysis of measured data from a six-cell CPV system demonstrate the benefits of Δ-conversion under realistic scenarios. Experimental results from prototype systems show up to 31% power benefits in the presence of mismatches.

Actuellement la nécessité des systèmes d'alimentation d'énergie, capables d'assurer un fonctionnement stable dans des domaines de fonctionnement assez larges avec des bonnes performances dynamiques (rapidité du système, variations limitées de la tension de sortie en réponse aux perturbations de charge ou de tension d'alimentation), devient de plus en plus importante. De ce fait, cette thèse est orientée sur la commande des convertisseurs de puissance DC-DC représentés par des modèles hybrides.En tenant compte de la structure variable de ces systèmes à commutation, un modèle hybride permet de décrire plus précisément le comportement dynamique d'un convertisseur dans son domaine de fonctionnement. Dans cette optique, l'approximation PWA est utilisée afin de modéliser les convertisseurs DC-DC. A partir des modèles hybrides développés, on s'est intéressé à la stabilisation des convertisseurs au moyen des correcteurs à gains commutés élaborés sur la base de fonctions de Lyapunov PWQ, et à l'implantation d'une commande prédictive explicite, en considérant des contraintes sur l'entrée de commande. La méthode de modélisation et les stratégies de commande proposées ont été appliquées sur deux topologies : un convertisseur buck, afin de mieux maîtriser le réglage des correcteurs et un convertisseur flyback avec filtre d'entrée. Cette dernière topologie nous a permis de répondre aux difficultés du point de vue de la commande (comportement à déphasage non-minimal) rencontrées dans la majorité des convertisseurs DC-DC. Les performances des commandes élaborées ont été validées en simulation sur les topologies considérées et expérimentalement sur une maquette du convertisseur buck.

Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.

In recent years, smart gird has received much attention, and many researchers have devoted to home area network (HAN) to improve the efficiency of grid. This thesis proposes a bidirectional isolated DC-DC converter (Dual Active Bridge, DAB) with phase shift control to implement the concept of HAN. Li+Fe battery is used as storage device of the converter, and a bidirectional communication between Laboratory Virtual Instrumentation Engineering Workbench (LabVIEW) and Digital Signal Processor (DSP) is realized by CAN-bus. By setting the current command given by LabVIEW system, the converter is able to charge the Li+Fe battery with constant current and constant voltage method as well as discharge the Li+Fe battery with constant current. Operation principle of the converter and the associated loss are presented.

In this thesis a two-stage AC/DC/DC power converter is designed and implemented. The AC/DC input stage of the converter consists of the two&amp / #8211 / phase interleaved boost topology employing the average current mode control principle. The output stage consists of a zero voltage switching phase shifted full bridge (ZVS&amp / #8211 / PS&amp / #8211 / FB) DC/DC converter. For the input stage, main design goals are obtaining high input power factor, low input current distortion, and well regulated output dc voltage, and obtaining these attributes in a power converter with high power density. For the input stage, the interleaved structure has been chosen in order to obtain reduced line current ripple and EMI, reduced power component stresses, and improved power density. The control of the pre&amp / #8211 / regulator is provided by utilizing a new commercial monolithic integrated circuit, which provides interleaved continuous conduction mode power factor correction (PFC). The output stage is formed by utilizing the available prototype hardware of a ZVS&amp / #8211 / PS&amp / #8211 / FB DC/DC converter and mainly the system integration and controller design and implementation studies have been conducted. The converter small signal model is derived and utilizing its transfer function and employing voltage loop control, the output voltage regulator has been designed. The output voltage controller is implemented utilizing a digital signal processor (DSP). Integrating the AC/DC preregulator and DC/DC converter, a laboratory AC/DC/DC converter system with high overall performance has been obtained. The overall system performance has been verified via computer simulations and experimental results obtained from laboratory prototype.

In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.

This theses analyzes Cuk converter, that is one of the dc to dc switching converters. For continuous inductor current mode and discontinuous inductor current mode, stedy state operation is analysied. Characteristic parameters are determined. Through State Space Averge Models, Small Signal Models are obtained. Parasitic Resistance effects on steady state and small signal models are determined. Efficency of the switching converter is derived. Open loop transfer functions for continous and discontinuous inductor curret mode are obtained. Parmeters for small signal behaviour is determined and stability is analysied. Parasitic resistance effects on transfer functions is determined. Therotecial analysis are verified with a simulations of designed converter.

Switched mode power supplies (SMPS) are being extensively used in most power conversion processes. The analysis, design and modeling processes of hard-switched converters are mature, where the switching frequency was limited to a few 10's of kHz. The present direction of evolution m SMPS is towards higher efficiency and higher power density. These twin objectives demand high switching frequency and low overall losses. Soft switching results in practically zero switching losses and extends the switching frequency to 100's of kHz and beyond. This thesis presents novel variants of push-pull and half-bridge DC-DC converters with soft switching properties. The proposed topology uses two additional switches and two diodes. The additional switches introduce freewheeling intervals m the circuit and enable loss-less switching. Switch stress, control and small signal model are similar to hard-switched PWM converter. Synchronous rectifiers are used in the ZVS push-pull converter to achieve high efficiency. It is interesting to see that the drives for the synchronous rectifier device are practically the same as the additional switches. The contributions made in this thesis are 1) Idealized analysis and design methodology for the proposed converters. 2) Validation of the design through circuit simulation as well as prototypes - a 300kHz, 200W push-pull converter and a 300kHz, 640W half-bridge converter. 3) Closed loop control design for desired bandwidth and accuracy Verification of loop gain through network analyzer instrumental for the same The loop gain bandwidth achieved is about 30kHz for the push-pull converter and 20kHz for half-bridge converter. An appendix has been devoted to explain the use of network analyzer. Characterization of coil, transformer and capacitor are explained in detail. Measurement techniques for measuring the small signal parameters of power supply are also explained in the appendix.