As technology is advancing, larger and denser devices are being manufactured with shorter time to market requirements. Identifying and resolving problems in integrated circuits (ICs) are the main focus of the pre-silicon and post-silicon debug process. As indicated in the International Technology Roadmap for Semiconductors (ITRS), post-silicon debug is a major time consuming challenge that has significant impact on the development cycle of a new chip. Since it is difficult to acquire the internal signal values, conventional debug techniques typically involve performing a binary search for failing vectors and performing mechanical measurement with a probing needle. Silicon debug is a labor intensive task and requires much experience in validating the first silicon. Finding information about when (temporal) and where (spatial) failures occur is the key issue in post-silicon debug. Test vectors and test applications are run on first silicon to verify the functionality when it arrives. Scan chains and on-chip memories have been used to provide the valuable internal signal observation information for the silicon debug process. In this dissertation, a scan-based technique is presented to detect the circuit misbehavior without halting the system. A debugging technique that uses a trace buffer is introduced to efficiently store a series of data obtained by a two dimensional compaction technique. Debugging capability can be maximized by observing the right set of signals to observe. A method for an automated selection of signals to observe is proposed for efficient selection. Investigation in signal observability is further extended to signal controllability in test point insertion. Noble test point insertion techniques are presented to reduce the area overhead for test point insertion. / text

In this thesis, the first section will talk about how to implement the software development environment for 8bit microprocessor, including Compiler, Assembler, and Debugging mechanism etc. The design of Debugging mechanism is based on in-circuit emulator. In-circuit emulator is a common debugging technique for microprocessor. The designed ICE contains hardware implement and debugging software for it in this thesis. ICE hardware is a control circuit from TAP Controller, IEEE 1149.1 std. and it control the scan cells on the data bus. The Debugging software uses JTAG port, IEEE 1149.1 std., to insert debug instruction from PC to ICE hardware. In this thesis, the second section will focus on the process of integrating ICE hardware circuit and software debugger issued by two ways, our own design version and business suit debugging software support. The examples are not only integrating our LAB¡¦s 32bit microprocessor and ICE hardware, but also verifying software debugger to control ICE circuit by FPGA to prove above two methods are work.

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a framework that automatically generates random programs with user specified features. These programs are used to verify the correctness of the compiled hardware by comparing the hardware simulation results with the software execution results. This way, users can have a large number of benchmarks to test their algorithms for HLS without having to manually develop test programs. The tool also provides additional ways of analyzing performance of HLS tools. Rather than being a replacement, this technique should serve as a useful complement to existing manually constructed test suites. Together, they can provide more comprehensive verification and analysis for HLS tools.

Debugging in the System-on-a-Chip (SoC) environment is a challenge since it was hard to observe their signals on a chip. How to obtain the chip internal signals to help chip designers effective to verify and debug has become an important issue.It is impractical to observe their signals on output pins due to pin number limitation. The conventional solution is to embed a monitor within the hardware for capturing the signals in real time and storing them in a on-chip trace memory. This thesis shows how the embedded multi-resolution AXI Bus Tracer can enable users to achieve the SoC debugging and performance evaluation efficiently, and it can trace the AXI Signals on the AMBA 3.0 AXI environment. Users can dynamically adjust the tracking resolution during the program execution, and we also provide an effective encoding algorithm for compressing the trace data. With our trace analysis software, we provide the detail information ranging from detail signal waveforms to transaction level waveforms, and transfer the trace signals into Value Change Dump (VCD) file. We also show several pie charts to analyze the portion of transfer types. In our work, we provide a synthesizable hardware to embed SOC for capturing signals. Then traced information through decompress and analysis can make users analyze system debugging and performance evaluation.

Address trace compression represents that the address data, which are generated from the instruction fetch stage of the microprocessor, can be retrieved for later observation and analysis. This real time trace compression hardware is the primary component of real-time trace system. In this paper, we present how to design and implement this real-time address trace compressor. Address trace compressor is allowed to perform accurate, successive trace collection in an unlimited length and can be used in various embedded microprocessors without influencing the operation of the microprocessors. Also, it has abundant reconfigurable parameters that can be used to develop a cost-effective trace system. The experiment results show that this compressor can reach a higher compression ratio of 1:100. Hence, by utilizing this real-time compression technique, the trace depths of new trace system can be 20 times more than these existing in-circuit emulators.

System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance increase, more IPs (Intellectual Property) are integrated into a modern SoC. Developing such a complex SoC is challenging since the SoC has limited observability; modern SoCs usually leave limited spared I/O pins for debugging purpose due to cost consideration, making it hard to analyze the internal activities via the limited I/O pins. This hampers the SoC development. To ease the difficulty, we have implemented the SYS-SIP (National Sun Yat-Sen university's SoC Infrastructure IP's) to enable the SoC development in terms of verification, debugging, monitor ing, and performance tuning. The SYS-SIP consists of five members: Processor External Interrupt Verification Module (PEVM), ICE, processor tracer, bus tracer, and protocol checker. Each of them serves specific purposes in verification, debugging, monitoring, and performance tuning. The SYS-SIP can be applied at diffierent design stages: RTL, FPGA, and chip level. The results show that SYS-SIP eases the SoC development and shortens the time-to-market significantly.

Semiconductor manufacturing is complex. Companies strive to lead in the markets by delivering timely chips which are bug (a.k.a defect) free and have very low power consumption. The new research drives new features in chips. The case study research reported here is about the usability and productivity of the silicon debug software tools. Silicon debug software tools are a set of software used to find bugs before delivering chips to the customer. The study has an objective to improve usability and productivity of the tools, by introducing metrics. The results of the measurements drive a concrete plan of action. The GQM (Goal, Questions, Metrics) methodology was used to define and gather data for the measurements. The project was developed in two parts or phases. We took the measurements using the method over the two phases of the tool development. The findings from phase one improved the tool usability in the second phase. The lesson learnt is that tool usability is a complex measurement. Improving usability means that the user will use less of the tool help button; the user will have less downtime and will not input incorrect data. Even though for this study the focus was on three important tools, the same usability metrics can be applied to the remaining five tools. For defining productivity metrics, we also used the GQM methodology. A productivity measurement using historic data was done to establish a baseline. The baseline measurements identified some existing bottlenecks in the overall silicon debug process. We link productivity to time it takes for a debug tool user to complete the assigned task(s). The total time taken for using all the tools does not give us any actionable items for improving productivity. We will need to measure the time it takes for use of each tool in the debug process to give us actionable items. This is identified as future work. To improve usability we recommend making tools that are more robust to error handling and having good help features. To improve productivity we recommend getting data on where the user is spending most of the debug time. Then, we can focus on improving that time-consuming part of debug to make the users more productive. / text

This thesis proposes a automated test case generation technique for the aim of verifying/debugging High-level synthesis (HLS) tools. The work in this thesis builds a framework that automatically generates random programs with user specified features. These programs are used to verify the correctness of the compiled hardware by comparing the hardware simulation results with the software execution results. This way, users can have a large number of benchmarks to test their algorithms for HLS without having to manually develop test programs. The tool also provides additional ways of analyzing performance of HLS tools. Rather than being a replacement, this technique should serve as a useful complement to existing manually constructed test suites. Together, they can provide more comprehensive verification and analysis for HLS tools.

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.

<p>The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.</p><p>The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.</p><p>In the project 4 blocks has been designed:</p><p>The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.</p><p>The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.</p><p>A text terminal program for Linux has also been programmed for handling the PC side communication.</p><p>The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.</p><p>The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.</p>