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Post-silicon validation is an important step during the implementation flow of digital integrated circuits and systems. Most of the validation strategies are based on ad-hoc solutions, such as guidelines from best practices, decided on a case-by-case basis for a specific design and/or application domain. Developing systematic approaches for post-silicon validation can mitigate the productivity bottlenecks that have emerged due to both design diversification and shrinking implementation cycles. Ever since integrating on-chip memory blocks became affordable, embedded logic analysis has been used extensively for post-silicon validation. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed as an algorithmic problem a decade ago. Most of the proposed solutions focus on how to restore as much data as possible within a software simulator in order to facilitate the analysis of functional bugs, assuming that there are no electrically-induced design errors, e.g., bit- flips. In this thesis, first it is shown that analyzing the logic inconsistencies from the post-silicon traces can aid with the detection of bit-flips and their root-cause analysis. Furthermore, when a bit-flip is detected, a list of suspect nets can be automatically generated. Since the rate of bit-flip detection as well the size of the list of suspects depends on the debug data that was acquired, it is necessary to select the trace signals consciously. Subsequently, new methods are presented to improve the bit-flip detectability through an algorithmic approach to selecting the on-chip trace signals. Hardware assertion checkers can also be integrated on-chip in order to detect events of interest, as defined by the user. For example, they can detect a violation of a design property that captures a relationship between internal signals that is supposed to hold indefinitely, so long as no bit-flips occur in the physical prototype. Consequently, information collected from hardware assertion checkers can also provide useful debug information during post-silicon validation. Based on this observation, the last contribution from this thesis presents a novel method to concurrently select a set of trace signals and a set of assertions to be integrated on-chip. / Thesis / Doctor of Philosophy (PhD)

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA. / Ph. D.

Nowadays, static analysis is a helpful option for developers to ensure all the important properties of a developed application. But these analyses must be also developed and it is inevitable that sometimes they must be debugged to find and solve problems inside of the analyses themself. The debugging of static analyses might be more complicated because some popular analysis frameworks do not provide sufficient support for debugging. One of the widely used analysis frameworks is WALA. In this thesis, we thoroughly explored all the main features of WALA and determined possible points for better debugging support. For each of these points, we designed and implemented supporting infrastructure that should accelerate the process of debugging by avoiding the tedious manual effort needed for inspection and evaluation of the internal state of WALA. One kind of these points is the analysis configuration where we created an inspection system for class hierarchy and call graph that should detect common misconfiguration problems. The next point is the debugging of the data flow transfer functions, for which we created a visualizer of the running analysis over the subject program. This visualization is done within the Visual Studio Code editor. To connect the editor with the analysis we used Debug Adapter Protocol and...

This work details the implementation of a debugger for a small embedded RISC-V system. KTH uses an in-house designed microcontroller development board for computer and electronics design courses. The boards did not incorporate hardware debugging capabilities and no prior software implementation fulfilled the requirements for the specific target system. The debugger used a hybrid software and hardware approach for achievingbasic debugging features such as breakpoints, stepping and break signals. The hybrid approach repurposed the microcontrollers debug module to enable debugging with no external hardware. The debugger implementation met all of the requirements for being ableto be used in the intended educational setting, and had a limited footprint withregard to resource usage, but with room for further optimization. / Detta arbete beskriver implementationen av en debugger för ett mindre RISC-V system. KTH använder ett internt framtaget utvecklingskort med en mikrokontroller för kurser inom programmering för inbyggda system och elektronikdesign. Korten inkluderade inte stöd för hårdvarubaserad debugging och inga befintliga mjukvarulösningar mötte kraven för det specifika systemet. Debuggern använde en blandad hårdvaru- och mjukvarulösning för att uppnå debug-funktionalitet som brytpunkter, stegning och brytsignaler. Implementationen nyttjade den i mikrokontrollern inbyggda debugmodulen(debug module) för att tillgängliggöra debugging utan någon extern hårdvara. Implementationen mötte alla krav för att kunna användas i den tilltänkta studiemiljön, och hade en begränsad resursanvändning, men med rum för ytterligare optimeringar.

Configurable computing machines (CCMs) offer high-performance application acceleration with custom hardware. They are also dynamically reconfigurable and give significant internal visibility. Such features are useful throughout the design, debug, and deploy stages of CCM-based application development. However traditional, monolithic design tools do not offer adequate support for all of these development stages. This thesis describes a specification for a reconfigurable computing application framework (RCAF) which is more suitable for CCM application development. It also describes an implementation of such an RCAF. This RCAF improves the efficiency of application design and debugging. It also establishes an application architecture framework which helps to build up not only the hardware design, but also the application software and user interface. Applications built using this small, deployable RCAF may also perform significantly better due to the dynamic hardware reconfiguration features included with the RCAF.

This master's thesis is dedicated to the remote control of Android devices using the Android Debug bridge tool. Another essential part of the work is automated batch testing of Android applications. It focuses on individual tools (Android Debug Bridge, MonkeyRunner, logcat, Appium) needed to resolve this issue. It also describes a web framework Nette and other technologies that were used for the final design and implementation of information system.

Android is the most used operating system in the world, because of this the probability of an android device being acquired in an investigation is high. To begin to extract data from an android device you first need to gain access to it. Mechanisms like full system encryption can make this very difficult. In this paper, the advantages and disadvantages of different methods of gaining access and extracting data from an android device with an unlocked bootloader are discussed. Many users unlock the bootloader of their android device to gain a much greater level of control over it. Android forensics on a device without a unlocked bootloader is very limited. It is therefore interesting to study how you can extract data from an android device that doesn’t have this limitation to android forensics. A literature study is done on previous related research to gather methods for gaining access and extracting data. The methods collected are then tested by performing experiments on a Oneplus 3 android 9 and Oneplus 8 android 11. The research of this paper found that it is possible to perform a brute force attack within a reasonable time against a PIN of length 4-5 or pattern of length 4-6 on the lock screen of an android device. It found that you can optimise the attack by performing a dictionary attack by using public lists of the most used PIN codes. A list of all possible pattern combinations sorted and optimised for a dictionary attack is generated based on statistics of pattern starting location and length. A proof of concept is made by creating a copy of a fingerprint with common cheap materials to gain access through the fingerprint sensor. A device image were able to be extracted by using a root shell through Android Debug Bridge and common command-line tools. Memory forensics were performed by using Frida and was able to extract usernames, passwords, and emails from Google Chrome and Gmail. The custom recovery image TWRP was used to boot the device, gain root access, and was able to extract a full device image with common command-line tools. The results of the TWRP backup feature is also analysed. The results of the data extraction is then analysed manually and with Autopsy.

The aim of the work is the design and implementation of two circuit boards delivering learning platforms, which will consist of two separate circuit boards with ARM MCU and a programmable FPGA gate array that will be interconnectable and appropriately complemented by peripherals. These platforms will be developed by analysing current teaching and development platform solutions and then demonstrating on practical examples. The main benefit of this work should be update and simplification of existing equipment. At the same time, there is an emphasis on greater transparency of the whole solution, so that it is not too complicated for an aspiring student to familiarise himself with modern micro-controllers and programmable gate arrays and can link the simpler units into more complex ones, where the individual boards can be used as separate working units and their interconnection will provide a computationaly stronger yet more complex device.