Preference for smaller-sooner over larger-later rewards characterizes one type of impulsivity—impulsive choice. Impulsive choice is related to a number of maladaptive behaviors including substance abuse, pathological gambling, and poor health behaviors. As such, interventions designed to reduce impulsive choice may have therapeutic benefits. The purpose of this dissertation was to explore two methods to change nonhuman impulsive choice. In doing so, we hope to provide a baseline that future research can use to assess variables that are less amenable to human research (e.g., drug self-administration following reductions in impulsive choice). In Chapter 2, we failed to reduce nonhuman impulsive choice using working-memory training, a finding both inconsistent and consistent with the extant human literature. Chapters 3-5 sought to better understand a training regimen that generates large between-group differences in nonhuman impulsive choice—delay- and immediacy-exposure training. The results from Chapters 3 and 4 suggest that prolonged exposure to delayed food rewards produces large and long-lasting reductions in impulsive choice. Chapter 5 showed that the delay-exposure training effect can be obtained in fewer sessions than has previously been employed. A better understanding of the effects of delay-exposure training on nonhuman impulsive choice may have implications for the design and implementation of a human analog.

<p>Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products.</p><p>Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation.</p><p>The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics.</p><p>The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality.</p><p>In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.</p>

<p>The first part of the thesis (Part I) is devoted to find methods to describe transient behaviour of traffic processes, where the main emphasis is put on the description and analysis of excess periods and excess volumes of quite general stochastic processes. By assuming that traffic changes on different time scales, the transient characteristics such as excess periods could be important measures to describe periods of congestion on a communication link and moreover, the corresponding excess volume will represent lost information during such periods. Although the results obtained are of rather general nature, they provide some rather fundamental insight into transient characteristics of traffic processes. The distributions of the length of excess periods may then be expressed it terms of some excess probabilities that are related to the minimum of the process in the time interval considered. Similar relationsfor the excess volumes are harder to obtain and require the joint probability of the arrived volume and the minimum of the process in the same time interval.</p>

The first part of the thesis (Part I) is devoted to find methods to describe transient behaviour of traffic processes, where the main emphasis is put on the description and analysis of excess periods and excess volumes of quite general stochastic processes. By assuming that traffic changes on different time scales, the transient characteristics such as excess periods could be important measures to describe periods of congestion on a communication link and moreover, the corresponding excess volume will represent lost information during such periods. Although the results obtained are of rather general nature, they provide some rather fundamental insight into transient characteristics of traffic processes. The distributions of the length of excess periods may then be expressed it terms of some excess probabilities that are related to the minimum of the process in the time interval considered. Similar relationsfor the excess volumes are harder to obtain and require the joint probability of the arrived volume and the minimum of the process in the same time interval.

The demand for efficient and reliable high rate communication is ever increasing. In this thesis we study different challenges in such systems, and their possible solutions. A goal for many years has been to implement as much as possible of a radio system in the digital domain, the ultimate goal being so called software defined radio (SDR) where the inner workings of a radio standard can be changed completely by changing the software. One important part of an SDR receiver is the high speed analog-to-digital converter (ADC) and one path to reach this high speed is to use a number of parallel, time-interleaved, ADCs. Such ADCs are, however, sensitive to sampling instant offsets, DC level offsets and gain offsets. This thesis discusses estimators based on fractional-delay filters and one application of these estimmators is to estimate and calibrate the relative delay, gain, and DC level offset between the ADCs comprising the time interleaved ADC. In this thesis we also present a technique for carrier frequency offset (CFO) estimation in orthogonal frequency division multiplexing (OFDM) systems. OFDM has gone from a promising digital radio transmission technique to become a mainstream technique used in several current and future standards. The main attractive property of OFDM is that it is inherently resilient to multipath reflections because of its long symbol time. However, this comes at the cost of a relatively high sensitivity to CFO. The proposed estimator is based on locating the spectral minimas within so-called null or virtual subcarriers embedded in the spectrum.~The spectral minimas are found iteratively over a number of symbols and is therefore mainly useful for frequency offset tracking or in systems where an estimate is not immediately required, such as in TV or radio broadcasting systems. However, complexity-wise the estimator is relatively easy to implement and it does not need any extra redundancy beside a nonmodulated subcarrier. The estimator performance is studied both in a channel with additive white Gaussian noise and in a multipath frequency selective channel environment. Interpolators and decimators are an important part of many systems, e.g. radio systems, audio systems etc. Such interpolation (decimation) is often performed using cascaded interpolators (decimators) to reduce the speed requirements in different parts of the system. In a fixed-point implementation, scaling is needed to maximize the use of the available word lengths and to prevent overflow. In the final part of the thesis, we present a method for scaling of multistage interpolators/decimators using multirate signal processing techniques. We also present a technique to estimate the output roundoff noise caused by the internal quantization.

This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA). Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random local variations are growing rapidly in each technology generation. However, there is requirement of quantification of variation in silicon. We propose an all-digital circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form based on a reconfigurable ring oscillator structure. A test chip is fabricated in 65nm technology node to show the feasibility of the technique. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. The huge random delay variation in silicon motivates the inclusion of random local process parameters in delay model. In today’s low power design with multiple supply domain leads to non-uniform supply profile. The switching activity across the chip is not uniform which leads to variation of temperature. Accurate timing prediction motivates the necessity of Process, Voltage and Temperature (PVT) aware delay model. We use neural networks, which are well known for their ability to approximate any arbitrary continuous function. We show how the model can be used to derive sensitivities required for voltage and temperature scalable linear SSTA for an arbitrary voltage and temperature point. Using the voltage and temperature scalable linear SSTA on ISCAS 85 benchmark shows promising results with average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.65% and errors in predicting the 99% and 1% probability point are 1.31% and 1% respectively with respect to SPICE.

Data aggregation is an important technique in wireless sensor networks. The data are gathered together by data fusion routines along the routing path, which is called data-centralized routing. We propose a localized, Delay-bounded and Energy-efficient Data Aggregation framework(DEDA) based on the novel concept of DEsired Progress (DEP). This framework works under request-driven networks with realistic MAC layer protocols. It is based on localized minimal spanning tree (LMST) which is an energy-efficient structure. Besides the energy consideration, delay reliability is also considered by means of the DEP. A node’s DEP reflects its desired progress in LMST which should be largely satisfied. Hence, the LMST edges might be replaced by unit disk graph (UDG) edges which can progress further in LMST. The DEP metric is rooted on realistic degree-based delay model so that DEDA increases the delay reliability to a large extent compared to other hop-based algorithms. We also combine our DEDA framework with area coverage and localized connected dominating set algorithms to achieve two more resilient DEDA implementations: A-DEDA and AC-DEDA. The simulation results confirm that our original DEDA and its two enhanced variants save more energy and attain a higher delay reliability ratio than existing protocols.

Data aggregation is an important technique in wireless sensor networks. The data are gathered together by data fusion routines along the routing path, which is called data-centralized routing. We propose a localized, Delay-bounded and Energy-efficient Data Aggregation framework(DEDA) based on the novel concept of DEsired Progress (DEP). This framework works under request-driven networks with realistic MAC layer protocols. It is based on localized minimal spanning tree (LMST) which is an energy-efficient structure. Besides the energy consideration, delay reliability is also considered by means of the DEP. A node’s DEP reflects its desired progress in LMST which should be largely satisfied. Hence, the LMST edges might be replaced by unit disk graph (UDG) edges which can progress further in LMST. The DEP metric is rooted on realistic degree-based delay model so that DEDA increases the delay reliability to a large extent compared to other hop-based algorithms. We also combine our DEDA framework with area coverage and localized connected dominating set algorithms to achieve two more resilient DEDA implementations: A-DEDA and AC-DEDA. The simulation results confirm that our original DEDA and its two enhanced variants save more energy and attain a higher delay reliability ratio than existing protocols.

ABSTRACT THE EXAMINATION OF FACTORS THAT INFLUENCE TREATMENT SEEKING DELAY AMONG OLDER ADULTS DIAGNOSED WITH ACUTE MYOCARDIAL INFARCTION By Deonna S. Tanner Early diagnosis and treatment of acute myocardial infarction (AMI) can greatly reduce the morbidity and mortality associated with this condition. However, individuals, particularly older adults, delay seeking treatment for AMI symptoms. The purpose of this study was to examine the relationship of factors that influence pre-hospital delay in seeking treatment among older adults diagnosed with AMI. A descriptive, cross-sectional, comparative study design with a correlational component was used. Data were collected from 82 hospitalized older adults (60-80 years of age). For statistical analyses, older adults were divided into two groups. The shorter delay group delayed ≤ 120 minutes from the onset of symptoms (OS) and the longer delay group delayed > 120 minutes. Using the Common Sense Model as a guide, groups were compared on the following variables: internal influences (age, gender, race, history of AMI) and external influences (personal and professional support), cognitive representations of symptoms (symptom interpretation, perceived level of control, seriousness), and emotional representations of symptoms (anxiety and uncertainty). The majority of participants were retired/unemployed (64.6%) White men (82.9%) who were married (73.2%) with a mean age of 69.04 (± 5.82) years. The median delay time was 2.6 hours (range 0.5 - 432 hours). Participants experienced on average eight (± 3.86) symptoms (typical and atypical) with high levels of pain (M= 7.1 ± 3.4) and high state anxiety (M = 56.47 ± 10.37) at the time of the AMI. Findings show the only significant independent predictor of delay time was personal support. Being more certain that symptoms were heart related or having a previous AMI resulted in significantly shorter delay time (p <.05). Contacting a healthcare provider was not helpful for these older adults. Findings show factors influencing delay are challenging and complex, yet laypersons play an important role in the decision to seek treatment. Future research should include community-based educational programs focusing on atypical AMI symptoms and ways to increase the activation of emergency medical services soon after the OS.

Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products. Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation. The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics. The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality. In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.