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Mobilidade eletrônica em poços quânticos parabólicos de AlGaAs / Electron mobility in wide parabolic quantum wells of AlGaAsSeraide, Rodrigo Migotto 20 April 2001 (has links)
Neste trabalho estudamos as estruturas e as mobilidades eletrônicas em um sistema quase-bidimensional de poços quânticos parabólicos de AlxGa1-xAs dopados. Obtemos as auto-energias, as funções de onda e os perfis dos potencias de confinamento efetivo no sistema, através das soluções numéricas das equações de Schrödinger e de Poisson de forma autoconsistente. Em particular, estudamos as mobilidades quânticas e de transporte nestes sistemas. Devido a ocupação de várias subbandas nestes sistemas, as contribuições dos espalhamentos inter-subbandas para as mobilidades têm a mesma importância que os espalhamentos intra-subbandas. Obtemos as mobilidades de cada subbanda devido aos espalhamentos por impurezas doadoras e aceitadoras ionizadas e por potencial de liga. Analisamos os efeitos das distribuições de doadores dopados, de aceitadores de fundo e do potencial de gate externo / In this work we study the electronic structure and electron mobilities in doped wide parabolic quantum wells of AlxGa1-xAs. The subband energies, the wavefunctions, and the effective confining potential profile are obtained by studying selfconsistently the coupled Schrödinger and Poisson equations. Based on the numerical results of the electronic structure, we calculate the quantum and transport mobilities of the system. Usually several subbands are occupied in such systems and they are strongly coupled to each other, the intersubband interaction shows the same importance as the intrasubband one to the electronic transport. We study and analyze the electron mobility of each subband due to the ionized donor scattering and the alloy scattering. We also show the effect of ionized background acceptor impurity scattering
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An Electromechanical Synchronization of Driving Simulator and Adaptive Driving Aide for Training Persons with DisabilitiesBerhane, Rufael 24 March 2008 (has links)
Cars have become necessities of our daily life and are especially important to people with disability because they extend their range of activity and allow participation in a social life.
Sometimes driving a normal car is impossible for individuals with severe disability and they require additional driving aide. However, it is dangerous to send these individuals on the road without giving them special training on driving vehicles using an adaptive aide.
Nowadays there are a number of driving simulators that train disabled persons but none of them have joystick-enabled training that controls both steering, gas and break pedal. This necessitates the design of a method and a system which helps a person with disabilities learn how to operate a joystick-enabled vehicle, by using a combination of an advanced vehicle interface system, which is a driving aide known as Advanced Electronic Vehicle Interface Technology (AVEIT) and virtual reality driving simulator known as Simulator Systems International (SSI).
This thesis focuses on the mechanism that synchronizes both AVEIT and SSI systems. This was achieved by designing a mechanical and electrical system that serves as a means of transferring the action between the AVEIT and SSI system. The mechanical system used for this purpose consists of two coupler units attached to AVEIT and SSI each combined together by the electrical system. As the user operates the joystick, the action of AVEIT is transferred to the SSI system by the help of the electromechanical system. The design provides compatibility between the AVEIT and SSI system which makes them convenient for training persons with disability.
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Fabrication of nitride-based high electron mobility transistor biosensor to detect pancreatic cancer antigenHsu, Shi-Ya 31 July 2012 (has links)
Abstract
¡@¡@Biosensor chip has a lot of advantages, such as label-free, ultra-sensitive, highly selective, fast and real-time detection. Fabricating biosensor chip has great benefits for gene-detection, protein-detection, medical diagnosis and development of new medicine. This research will integrate the biomedical, chemistry, and physics, and also combined with biochemical technology and semiconductor technology to produce biosensor chip.
¡@¡@We use microelectronic semiconductor process technology to fabricate silicon nanowire field effect transistors (SiNW-FET). The source-drain current versus the voltage curve (Isd-Vsd) shows that the contact pad and the silicon nanowire form ohmic contact. And then we use chemical surface modification technologies to modified biotin on SiNW-FET to detect streptavidin.
¡@¡@In addition, we also grow AlGaN/GaN film by MBE, and fabricate nitride¡Vbased high electron mobility transistor (HEMT) by microelectronic semiconductor process technology. In this study, we apply HEMT in biosensor for pancreatic cancer marker CA19-9 antigen. And we modify pancreatic cancer marker CA19-9 antibody on the biosensor chip surface to detect pancreatic cancer marker CA19-9 antigen molecule.
¡@¡@Most of biomolecules are with weak charges, which can form chemical gating effect and change the conductance of p-type SiNW. And according to the streptavidin microfluidic measurement of biotin-modified SiNW-FET, the detection limit of streptavidin was 10-9 M. And the detection limit of pancreatic cancer marker CA19-9 antigen for N-HEMT biosensor was 150 U/mL.
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Feasibility study of III-nitride-based transistors grown by ammonia-based metal-organic molecular beam epitaxyBillingsley, Daniel D. 14 June 2010 (has links)
III-nitrides are a promising material system with unique material properties, which allows them to be utilized in a variety of semiconductor devices. III-nitrides grown by NH3-MOMBE are typically grown with high carbon levels (> 1021 cm-3) as a result of the incomplete surface pyrolysis of the metal-organic sources. Recent research has involved the compensating nature of carbon in III-nitrides to produce semi-insulating films, which can provide low-leakage buffer layers in transistor devices. The aim of this work is to investigate the possibility of forming a 2DEG, which utilizes the highly carbon-doped GaN layers grown by NH3-MOMBE to produce low-leakage buffer layers in the fabrication of HEMTs. These low leakage GaN buffers would provide increased HEMT performance, with better pinch-off, higher breakdown voltages and increased power densities. Additionally, methods of controlling and/or reducing the incorporation of carbon will be undertaken in an attempt to broaden the range of possible device applications for NH3-MOMBE. To realize these transistor devices, optimization and improved understanding of the growth conditions for both GaN and AlGaN will be explored with the ultimate goal of determining the feasibility of III-nitride transistors grown by NH3-MOMBE.
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High Power GaN/AlGaN/GaN HEMTs Grown by Plasma-Assisted MBE Operating at 2 to 25 GHzWaechtler, Thomas, Manfra, Michael J, Weimann, Nils G, Mitrofanov, Oleg 27 April 2005 (has links) (PDF)
Heterostructures of the materials system GaN/AlGaN/GaN were grown by molecular beam epitaxy on 6H-SiC substrates and high electron mobility transistors (HEMTs) were fabricated. For devices with large gate periphery an air bridge technology was developed for the drain contacts of the finger structure. The devices showed DC drain currents of more than 1 A/mm and values of the transconductance between 120 and 140 mS/mm. A power added efficiency of 41 % was measured on devices with a gate length of 1 µm at 2 GHz and 45 V drain bias. Power values of 8 W/mm were obtained. Devices with submicron gates exhibited power values of 6.1 W/mm (7 GHz) and 3.16 W/mm (25 GHz) respectively. The rf dispersion of the drain current is very low, although the devices were not passivated. / Heterostrukturen im Materialsystem GaN/AlGaN/GaN wurden mittels Molekularstrahlepitaxie auf 6H-SiC-Substraten gewachsen und High-Electron-Mobility-Transistoren (HEMTs) daraus hergestellt. Für Bauelemente mit großer Gateperipherie wurde eine Air-Bridge-Technik entwickelt, um die Drainkontakte der Fingerstruktur zu verbinden. Die Bauelemente zeigten Drainströme von mehr als 1 A/mm und Steilheiten zwischen 120 und 140 mS/mm. An Transistoren mit Gatelängen von 1 µm konnten Leistungswirkungsgrade (Power Added Efficiency) von 41 % (bei 2 GHz und 45 V Drain-Source-Spannung) sowie eine Leistung von 8 W/mm erzielt werden. Bauelemente mit Gatelängen im Submikrometerbereich zeigten Leistungswerte von 6,1 W/mm (7 GHz) bzw. 3,16 W/mm (25 GHz). Die Drainstromdispersion ist sehr gering, obwohl die Bauelemente nicht passiviert wurden.
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Mobilidade eletrônica em poços quânticos parabólicos de AlGaAs / Electron mobility in wide parabolic quantum wells of AlGaAsRodrigo Migotto Seraide 20 April 2001 (has links)
Neste trabalho estudamos as estruturas e as mobilidades eletrônicas em um sistema quase-bidimensional de poços quânticos parabólicos de AlxGa1-xAs dopados. Obtemos as auto-energias, as funções de onda e os perfis dos potencias de confinamento efetivo no sistema, através das soluções numéricas das equações de Schrödinger e de Poisson de forma autoconsistente. Em particular, estudamos as mobilidades quânticas e de transporte nestes sistemas. Devido a ocupação de várias subbandas nestes sistemas, as contribuições dos espalhamentos inter-subbandas para as mobilidades têm a mesma importância que os espalhamentos intra-subbandas. Obtemos as mobilidades de cada subbanda devido aos espalhamentos por impurezas doadoras e aceitadoras ionizadas e por potencial de liga. Analisamos os efeitos das distribuições de doadores dopados, de aceitadores de fundo e do potencial de gate externo / In this work we study the electronic structure and electron mobilities in doped wide parabolic quantum wells of AlxGa1-xAs. The subband energies, the wavefunctions, and the effective confining potential profile are obtained by studying selfconsistently the coupled Schrödinger and Poisson equations. Based on the numerical results of the electronic structure, we calculate the quantum and transport mobilities of the system. Usually several subbands are occupied in such systems and they are strongly coupled to each other, the intersubband interaction shows the same importance as the intrasubband one to the electronic transport. We study and analyze the electron mobility of each subband due to the ionized donor scattering and the alloy scattering. We also show the effect of ionized background acceptor impurity scattering
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Développement et caractérisation de modules Technologiques sur semiconducteur GaN : application à la réalisation de cathodes froides et de transistor HEMT AlGaN/GAN / Development and characterization of technological modules based on III-V (AlGaN/GaN) semiconductor for the realisation of AlGaN/GaN HEMTs and cold CathodesMalela-Massamba, Ephrem 17 June 2016 (has links)
Les travaux présentés dans ce manuscrit sont axés sur le développement et la caractérisation de modules technologiques sur semiconducteurs à large bande interdite à base de nitrure de gallium (GaN), pour la réalisation de transistors et de cathodes froides. Ils ont été réalisés au sein du laboratoire III-V lab, commun aux entités : Alcatel - Thales - CEA Leti. Notre projet de recherche a bénéficié d'un soutien financier assuré par Thales Electron Devices (TED) et l'Agence Nationale de la Recherche ( ANR ). Concernant les transistors HEMT III-N, nos investigations se sont focalisées sur le développement des parties actives des transistors, incluant principalement la structuration des électrodes de grilles, l'étude de la passivation des grilles métalliques, ainsi que l'étude de diélectriques de grille pour la réalisation de structures MIS-HEMT.Les transistors MOS-HEMT « Normally-off » réalisés présentent des performances comparables à l'état de l'art, avec une densité de courant de drain maximum comprise entre 270 mA et 400 mA / mm, un ratio ION / IOFF > 1100, et des tensions de claquage > 200V. Les tensions de seuil sont comprises entre + 1,8 V et + 4 V. Nos contributions au développement des cathodes froides ont permis de démontrer une première émission dans le vide à partir de cathodes GaN, avec une densité de courant maximale de 300 µA / cm2 pour une tension de polarisation de 40 V / The results presented in this manuscript relate to technological developments and device processing on wide bandgap III-N semiconductor materials. They have been focused on III-N HEMT transistors and GaN cold cathodes. They have been realised within the III-V lab, which is a common entity between: Alcatel - Thales - CEA Leti. They have been financially supported by Thales Electron Devices company (TED) and the French National Research Agency ( ANR ). Regarding III-N HEMTs, our investigations have been focused on the development of device gate processing, which includes : the structuration of gate electrodes, the study of device passivation, and the realization of Metal-Insulator-Semiconductor High Mobility Electron Transistors ( MIS-HEMTs ). The “ Normally-off ” MOS-HEMT structures we have realized exhibit performances comparable to the state of the art, with a maximum drain current density between 270 and 400 mA / mm, a ION / IOFF ratio > 1.100, and a breakdown voltage > 200V. The threshold voltage values range between + 1,8 V and + 4V. We have also been able to demonstrate prototype GaN cold cathodes providing a maximum current density of 300 µA / cm2, emitted in vacuum for a bias voltage around 40 V
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Robustness and Stability of Gallium Nitride Transistors in Dynamic Power SwitchingSong, Qihao 16 September 2024 (has links)
Wide-bandgap gallium nitride (GaN) high electron mobility transistors (HEMTs) are gaining increased adoption in applications like mobile electronics and data centers. Benefitting from the high channel mobility and the high breakdown field of GaN, GaN power HEMTs enable low specific on-resistance and small capacitance and thus become attractive for high-frequency applications. In addition, most commercial GaN power HEMTs are fabricated on Si substrates up to 8 inches, allowing for a remarkable cost advantage. However, a by-product of the low-cost GaN-on-Si wafer (and conductive Si substrate) is the high voltage drop and high electric field (E-field) in the GaN buffer layers and transition layers sandwiched between the GaN channel and Si substrate. To boost the vertical blocking capability and minimize the leakage current, the GaN buffer layer is usually doped with carbon or iron, which can introduce complex carrier traps. This can further lead to the dynamic shifts of various parameters in GaN-on-Si HEMTs, which can cause their stability and robustness issues in practical circuit operations.
This dissertation work studies the robustness and stability of GaN power HEMTs in dynamic power switching. The structures of most GaN power devices are fundamentally different from Si or Silicon Carbide (SiC) power devices, leading to numerous open questions on GaN power device robustness and stability. Simple equipment-level static characterization may not reflect the real device characteristics in circuit-level operation. Based on the relevance between the stress condition and the device's safe operating area (SOA), this dissertation is divided into two parts. In each part, two representative GaN power devices, the standalone GaN HEMT, and the GaN-Si cascode HEMT, are studied.
The dissertation's first half discusses the GaN HEMT behavior outside of SOA, with a focus on the robustness of GaN HEMTs in overvoltage power switching. This focus is motivated by the lack of avalanche capability of GaN HEMTs, which is a unique device physics distinct from SiC/Si power transistors. Instead of withstanding the surge energy through avalanching, GaN HEMTs rely on their high breakdown voltage margin to withstand the surge energy, which can trigger new degradation and failure mechanisms. Therefore, investigating the GaN HEMTs' robustness in overvoltage switching is of great interest.
The robustness study begins with a standalone depletion-mode (D-mode) MIS (Metal-Insulator-Semiconductor) HEMT in an overvoltage hard-switching. The device is found to show a decreased threshold voltage and increased saturation current after stress. These parametric shifts increase as switching cycles increase but reach a saturation point before one million cycles. The root cause is believed to be the impact-ionization-generated holes trapped underneath the insulated gate. This is verified by the physics-based TCAD (Technology Computer-Aided Design) simulation. After the stress, MIS-HEMT cannot fully recover naturally. Applying at positive gate-to-source bias (VGS) is found to be able to accelerate the threshold voltage recovery but not the saturation current recovery, while a 50-V substrate bias is shown to fully recover both parameters. These findings provide new insight into the hole trapping/de-trapping dynamics and the benefits of substrate voltage control in GaN MIS-HEMTs.
Then, a cascode GaN HEMT, which contains a D-mode GaN MIS-HEMT and an enhancement-mode (E-mode) Si MOSFET, is studied similarly in overvoltage stress produced by an inductive switching circuit. Parametric shifts are found in cascode GaN HEMTs, including the unstable breakdown voltage and increased on-resistance. The crosstalk between Si MOSFET and GaN HEMT is believed to account for these parametric shifts. A decapsulated device is developed based on the commercial part to monitor the Si MOSFET behavior. Si MOSFET is found to avalanche during the overvoltage switching. The parametric shifts are believed to be due to the avalanche-generated electrons, which are injected into the GaN HEMTs and trapped in the GaN buffer layer. These electron traps alter the E-field distribution of the GaN HEMT and induce parametric shifts.
The second half of the dissertation focuses on the GaN HEMT's stability inside the SOA, with a focus on the non-ideal power loss generated in high-frequency switching. The output capacitance (COSS) loss has recently been found to be the dominant loss in soft switching, which is the loss associated with GaN HEMT's COSS when it is charged and discharged. This process should be lossless for an ideal capacitor, but GaN HEMT experiences a hysteresis COSS loss during each charging-discharging cycle due to the COSS instability in dynamic power switching.
The COSS loss study starts with an accurate and easy-to-implement test platform, which is proven to have good robustness and repeatability. The measured COSS loss of different types of GaN HEMTs is modeled, followed by the investigation of the COSS loss origin. TCAD simulation reveals the fundamental role of trappings in the cause of COSS loss in standalone GaN HEMTs. For the cascode GaN HEMT, two additional loss mechanisms are involved as compared to the standalone GaN HEMTs: Si avalanche energy loss and GaN early turn-on loss. This makes cascode GaN HEMT experiences much higher COSS loss than standalone GaN HEMTs. The COSS loss of cascode GaN HEMT is quantitively analyzed, and a mitigation strategy is proposed for suppressing the COSS loss of cascode GaN HEMTs.
Then, a circuit-level method is proposed to reduce the COSS loss of standalone GaN HEMT by dynamically tuning the substrate bias, which is verified with a standalone D-mode GaN HEMT. The Si substrate bias can follow the drain voltage in a certain ratio by tuning the capacitance ratio between the drain, substrate, and source. It is found that with a substrate bias of 1/4 to 1/2 of the drain voltage, the COSS loss can be reduced by 86%. This result removes a critical roadblock for deploying GaN HEMTs in high-frequency, soft-switching applications.
Finally, the COSS loss of similarly rated Si and SiC power transistors is characterized using the developed test platform. The capability of the setup is further broadened to testing power diodes. Some similarities and distinctions are found in the COSS loss behavior between GaN HEMTs and Si/SiC devices. Also, an EDISS validation process is provided for the UIS-based method in an operating class-E converter, verifying the effectiveness and accuracy of the proposed method. This provides important references for selecting the optimal power devices for high-frequency applications. / Doctor of Philosophy / Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are reshaping the power electronics field. They have become increasingly popular in many applications like smartphones, electric vehicles, and data centers. They offer smaller on-resistance and can handle higher voltages compared to traditional silicon-based devices. GaN transistors are built on large-diameter silicon substrates, making them cost-effective but can lead to unique stability and robustness issues.
This dissertation investigates the stability and robustness of GaN power HEMTs in high-voltage and high-frequency power switching. Based on the relevance of the studied stress to the device safe-operating-area, the discussion is divided into two parts:
The first part looks at how GaN transistors handle situations where they are pushed beyond their safe operating limits, such as during power surges and overvoltage events. These transistors are found to experience changes in their electrical properties after being stressed, which might affect their performance across their lifetime. In addition to unveiling the physics and evolution of such parametric shifts, this work also discovers ways to recover the device parameters and maintain the device functionality.
The second part of the research focuses on the stability and non-ideal power loss of GaN transistors within their safe operating area. The high-frequency soft-switching application is being investigated, as it has become a common trend for future power electronics. The study reveals that GaN transistors can produce additional power loss due to the intrinsic electrical instabilities. In addition to unveiling the key impact factors and physics of this loss, this work also develops device designs to suppress this non-ideal power loss significantly, improving the device efficiency in high-frequency applications.
Overall, this work provides valuable insights into improving the robustness and efficiency of GaN transistors, which provide guidelines and insights for GaN designers and users to achieve optimal device and system performance.
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Low Noise Amplifiers using highly strained InGaAs/InAlAs/InP pHEMT for implementation in the Square Kilometre Array (SKA)Mohamad Isa, Muammar Bin January 2012 (has links)
The Square Kilometre Array (SKA) is a multibillion and a multinational science project to build the world’s largest and most sensitive radio telescope. For a very large field of view, the combined collecting area would be one square kilometre (or 1, 000, 000 square metre) and spread over more than 3,000 km wide which will require a massive count of antennas (thousands). Each of the antennas contains hundreds of low noise amplifier (LNA) circuits. The antenna arrays are divided into low, medium and high operational frequencies and located at different positions to boost up the telescope’s scanning sensitivity.The objective of this work was to develop and fabricate fully on-chip LNA circuits to meet the stringent requirements for the mid-frequency array from 0.4 GHz to 1.4 GHz of the SKA radio astronomy telescope using Monolithic Microwave Integrated Circuit technology (MMIC). Due to the number of LNA reaching figures of millions, the fabricated circuits were designed with the consideration for low cost fabrication and high reliability in the receiver chain. Therefore, a relaxed optical lithography with Lg = 1 µm was adopted for a high yield fabrication process.Towards the fulfilment of the device’s low noise characteristics, a large number of device designs, fabrication and characterisation of InGaAs/InAlAs/InP pHEMTs were undertaken. These include optimisations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics were further improved by a combination of judicious epitaxial growth and manipulation of materials’ energy gaps. An attempt to increase the device breakdown voltage was also employed by incorporating Field Plate structure at the gate terminal. This yielded the devices with improvements in the breakdown voltage up to 15 V and very low gate leakage of 1 µA/mm, in addition to high transconductance (gm) characteristic. Fully integrated double stage LNA had measured NF varying from 1.2 dB to 1.6 dB from 0.4 GHz to 1.4 GHz, compared with a slightly lower NF obtained from simulation (0.8 dB to 1.1 dB) across the same frequency band.These are amongst the attractive device properties for the implementation of a fully on-chip MMIC LNA circuits demonstrated in this work. The lower circuit’s low noise characteristic has been demonstrated using large gate width geometry pHEMTs, where the system’s noise resistance (Rn) has successfully reduced to a few ohms. The work reported here should facilitate the successful implementation of rugged low noise amplifiers as required by SKA receivers.
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Conception d’une nouvelle génération de redresseur Schottky de puissance en Nitrure de Gallium (GaN), étude, simulation et réalisation d’un démonstrateur / Design of a new generation of Gallium Nitride Schottky power rectifier, study, simulation and realization of a demonstratorSouguir-Aouani, Amira 16 December 2016 (has links)
Il y a actuellement un intérêt croissant pour la construction des dispositifs électroniques à semiconducteur pour les applications domotiques. La technologie des semiconducteurs de puissance a été essentiellement limitée au silicium. Récemment, de nouveaux matériaux ayant des propriétés supérieures sont étudiés en tant que remplaçants potentiels, en particulier : le nitrure de gallium et le carbure de silicium. L'état actuel de développement de la technologie 4H-SiC est beaucoup plus mature que pour le GaN. Cependant, l'utilisation de 4H-SiC n’est pas une solution économiquement rentable pour la réalisation des redresseurs Schottky 600 V. Les progrès récents dans le développement des couches épitaxiées de GaN de type n sur substrat Si offrent de nouvelles perspectives pour le développement des dispositifs de puissance à faible coût. C’est dans ce cadre que ma thèse s’inscrit pour réaliser avec ce type de substrat, un redresseur Schottky de puissance avec un calibre en tension de l’ordre de 600V. Deux architectures de redresseurs sont exposées. La première est une architecture pseudo-verticale proposée dans le cadre du projet G2ReC et la deuxième est une architecture latérale à base d’hétérojonction AlGaN/GaN obtenue à partir d'une structure de transistor HEMT. L’optimisation de ces deux dispositifs en GaN est issue de simulation par la méthode des éléments finis. Dans ce cadre, une adaptation des modèles de simulation à partir des paramètres physiques du GaN extraits depuis la littérature a été effectuée. Ensuite, une étude d’influence des paramètres géométriques et technologiques sur les propriétés statiques en direct et en inverse des redresseurs a été réalisée. Enfin, des structures de tests ont été fabriquées et caractérisées afin d’évaluer et d’optimiser le caractère prédictif des simulations par éléments finis. Ces études nous ont conduit à identifier l'origine des limites des structures de première génération et de définir de nouvelles structures plus performantes. / There is increasing interest in the fabrication of power semiconductor devices in home automation applications. Power semiconductor technology has been essentially confined to Si. Recently, new materials with superior properties are being investigated as potential replacements, in particular silicon carbide (SiC) and gallium nitride (GaN). The current state of development of SiC technology is much more mature than for GaN. However, the use of 4H-SiC is not a cost effective solution for realizing a medium and high voltage Schottky diode. Recent advances on the development of thick n-type GaN epilayers on Si substrate offer new prospects for the development of a low-cost Schottky rectifiers for at least medium voltage range 600 V. In the context of our thesis, two types of GaN based rectifier architectures have been studied. The first one is a pseudo-vertical architecture proposed during previous G2ReC project. The second one has a lateral structure with AlGaN/GaN heterojunction, derived from a HEMT structure. The optimization of the Schottky rectifiers has been achieved by finite element simulations. As a first step, the models are implemented in the software and adjusted with the parameters described in the literature. The influence of the geometrical and physical parameters on the specific on-resistance and on the breakdown voltage has been analysed. Finally, the test devices have been realized and characterized to optimize and to validate the parameters of these models. These studies lead to identify the limits of the structures and create a new generation of powerful structures.
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