Le développement du système électronique de puissance dans le transport électrique est poursuivi sous la forme de convertisseurs de puissance à haut rendement impliquant une topologie complexe.Bien que l'analyse et le contrôle d'un tel système soient souvent une tâche difficile en raison de l'environnement haute tension et haut courant, la simulation hardware-in-the-loop (HILs) offre un moyen sûr et rapide d'évaluer la stratégie de contrôle en simulant l'environnement externe du contrôleur dans le système embarqué.Au cours du processus, il y a deux exigences que nous devons relever dans le cadre de temps réel (i) Le processus de calcul doit être terminé avant que l'impulsion de déclenchement suivante de l'horloge en temps réel n'arrive; (ii) La latence dans le simulateur est assez petite pour être ignorée. Les périodes d'échantillonnage et de simulation dans les simulateurs basés sur CPU sont plus de 1 microseconde, il est difficile de prendre en compte l'ensemble des événements des commutateurs dans les systèmes d'entraînement modernes.En revanche, les FPGA (Field Programmable Gate Arrays) fournissent non seulement une vitesse d'échantillonnage rapide mais aussi une alternative viable pour accélérer le simulateur en temps réel. Cependant, la mise en œuvre d’un système électronique de puissance complexe dans les FPGA est l'une des limitations. Ainsi, dans cette thése, nous ferons des recherches sur la simulation en temps réel à base de FPGA avec la tentative de résoudre le problème en résolvant les questions suivantes,1.Comment pourrions-nous partitionner le système électronique de puissance et l'implémenter dans FPGA?2.Comment pouvons-nous tirer parti des fonctionnalités FPGA pour accélérer le processus de résolution de circuit3.Comment pourrions-nous optimiser les performances du FPGA?4.Comment exprimer la caractéristique de commutation non linéaire du système électronique de puissance dans le FPGA?La première question concerne la caractéristique hybride à l'intérieur du système électronique de puissance. Nous avons proposé une nouvelle méthode nodale et un solveur matriciel basé sur la décomposition de Cholesky essayant de garder la topologie du circuit fixe et de traiter chaque élément de commutation et de circuit indépendamment. La deuxième question est celle de savoir comment obtenir des approximations pour toutes sortes d’Équation différentielle (ODE). Nous avons utilisé une série de solveurs ODE parallèles pour accélérer le processus de résolution. La troisième question est d'utiliser des outils de synthèse de haut niveau (HLS) pour optimiser les performances du FPGA. De tels outils sont utilisés pour développer des unités de calcul haute performance pour des applications de simulation en temps réel. Enfin, afin de rechercher l'impact de la caractéristique de commutation non linéaire sur le système électronique de puissance, nous avons proposé un modèle IGBT ultra-rapide avec un temps de calcul en nanosecondes dans le FPGA.Dans l'ensemble, les méthodes présentées contribuent au développement du simulateur en temps réel par FPGA pour le système de transport électrique de trois façons: réduire le temps de calcul des matrices, proposer un solveur ODE parallèle dans le FPGA et optimiser les performances du FPGA. / The development of power electronic system in electrical transportation is being pursued in the form of high-efficiency power converters involving complex topology. Although analysis and control of such system is often a difficult task due to the high-voltage and high-current environment, the hardware-in-the-loop simulation (HILs) offers a time-saving and safe way to evaluate the control strategy by simulating the external environment of a controller in the embedded system.During the process, there are two requirements that we have to meet in the context of racing against real-time: (i) the computation process is necessary to the end before the next trigger impulse from the real-time clock arrives (ii) the latency in the simulator is small enough to ignore. The sampling and simulation period in today’s CPU-based HIL simulators can barely go under 1 us, it is hard to take into accounts the entire switch event from PWM (Pulse Width Modulation) in modern power drive systems. In contrast, Field Programmable Gate Arrays (FPGAs) provide not only an ultra-fast sampling speed but also a viable alternative for speeding up the real-time simulator. However, the implementing the complex power electronic system on FPGAs is one of the limitations in real time simulation. Thus, in this these, we will research the FPGA-based real-time simulation with the attempt to solve the following questions,1.How could we partition power electronic system and implement it in FPGA?2.How do we leverage FPGA features to accelerate circuit?3.How could we optimize the performance of FPGA?4.How do we express the nonlinear switch characteristic of power electronic system in the FPGA?The first question is about the hybrid characteristic inside the power electronic system. In the paper, we proposed a novel nodal method and a matrix solver based on Cholesky Decomposition trying to keep the circuit topology fixed and treat each switch and circuit element independently. The second question is one that how to obtain approximations for all kind of ordinary differential equations (ODEs). We utilized a series of parallel ODE solver to accelerate the solving process and deal with the stiff problem. The third question is to use high-level synthesis (HIL) tools to optimize the performance of FPGA. Such tools are employed for developing high-performance computing units, designated hereafter as hardware solvers (HS), for real-time simulation applications. At last, in order to research the impact of nonlinear switch characteristic on the power electronic system, we proposed an ultra-fast IGBT model with a calculation time in nanoseconds in the FPGA.Overall, the presented methods contribute to the development of FPGA-based real-time simulator in three ways: reducing the calculation time of matrix solving process, proposing parallel ODE solver in the FPGA and optimizing the performance of FPGA. Thus, with the FPGA solver we built, the model of power electronic system for electrical transportation can be solved within 50 nanoseconds in high accuracy.

Advances in microelectronics allow the integration of more andmore functionality on a single chip. Emerging system-on-a-chiparchitectures include a large amount of heterogeneous componentsand are of increasing complexity. Applications using thesearchitectures require many low-level details in order to yield anefficient implementation. On the other hand constanttime-to-market pressure on electronic systems demands a shortdesign process that allows to model a system at a highabstraction level, not taking low-level implementation detailsinto account. Clearly there is a significant abstraction gapbetween an ideal model for specification and another one forimplementation. This abstraction gap has to be addressed bymethodologies for electronic system design. This thesis presents the ForSyDe (Formal System Design)methodology, which has been developed with the objective to movesystem design to a higher level of abstraction and to bridge theabstraction gap by transformational design refinement. ForSyDe isbased on carefully selected formal foundations. The initialspecification model uses a synchronous model of computation,which separates communication from computation and has anabstract notion of time. ForSyDe uses the concept of processconstructors to implement the synchronous model, to allow fordesign transformation and the mapping of a refined model onto thetarget architecture. The specification model is refined into adetailed implementation model by the stepwise application ofwell-defined design transformation rules. These rules are eithersemantic preserving or they inflict a design decision modifyingthe semantics. These design decisions are used to introduce thelow-level implementation details that are needed for an efficientimplementation. The implementation model is mapped onto thecomponents of the target architecture. At present ForSyDe modelscan be mapped onto VHDL or C/C++ in order to allow commercialtools to generate custom hardware or sequential software. Thethesis uses a digital equalizer to illustrate the concepts andpotential of ForSyDe. Electronic System Design, Hardware/Software Co-Design,Electrical Engineering

Today's advanced digital devices are enormously complex and incorporate many functions. In order to capture the system functionality and to be able to analyze the needs for a final implementation more efficiently, the entry point of the system development process is pushed to a higher level of abstraction. System level design methodologies describe the initial system model without considering lower level implementation details and the objective of the design development process is to introduce lower level details through design refinement. In practice this kind of refinement process may entail non-semantic-preserving changes in the system description, and introduce new behaviors in the system functionality. In spite of new behaviors, a model formed by the refinement may still satisfy the design constraints and to realize the expected system. Due to the size of the involved models and the huge abstraction gap, the direct verification of a detailed implementation model against the abstract system model is quite impossible. However, the verification task can be considerably simplified, if each refinement step and its local implications are verified separately. One main idea of the Formal System Design (ForSyDe) methodology is to break the design process into smaller refinement steps that can be individually understood, analyzed and verified. The topic of this thesis is the verification of refinement steps in ForSyDe and similar methodologies. It proposes verification attributes attached to each non-semantic-preserving transformation. The attributes include critical properties that have to be preserved by transformations. Verification properties are defined as temporal logic expressions and the actual verification is done with the SMV model checker. The mapping rules of ForSyDe models to the SMV language are provided. In addition to properties, the verification attributes include abstraction techniques to reduce the size of the models and to make verification tractable. For computation refinements, the author defines the polynomial abstraction technique, that addresses verification of DSP applications at a high abstraction level. Due to the size of models, predefined properties target only the local correctness of refined design blocks and the global influence has to be examined separately. In order to compensate the influence of temporal refinements, the thesis provides two novel synchronization techniques. The proposed verification and synchronization techniques have been applied to relevant applications in the computation area and to communication protocols. / QC 20100816

<p>Advances in microelectronics allow the integration of more andmore functionality on a single chip. Emerging system-on-a-chiparchitectures include a large amount of heterogeneous componentsand are of increasing complexity. Applications using thesearchitectures require many low-level details in order to yield anefficient implementation. On the other hand constanttime-to-market pressure on electronic systems demands a shortdesign process that allows to model a system at a highabstraction level, not taking low-level implementation detailsinto account. Clearly there is a significant abstraction gapbetween an ideal model for specification and another one forimplementation. This abstraction gap has to be addressed bymethodologies for electronic system design.</p><p>This thesis presents the ForSyDe (Formal System Design)methodology, which has been developed with the objective to movesystem design to a higher level of abstraction and to bridge theabstraction gap by transformational design refinement. ForSyDe isbased on carefully selected formal foundations. The initialspecification model uses a synchronous model of computation,which separates communication from computation and has anabstract notion of time. ForSyDe uses the concept of processconstructors to implement the synchronous model, to allow fordesign transformation and the mapping of a refined model onto thetarget architecture. The specification model is refined into adetailed implementation model by the stepwise application ofwell-defined design transformation rules. These rules are eithersemantic preserving or they inflict a design decision modifyingthe semantics. These design decisions are used to introduce thelow-level implementation details that are needed for an efficientimplementation. The implementation model is mapped onto thecomponents of the target architecture. At present ForSyDe modelscan be mapped onto VHDL or C/C++ in order to allow commercialtools to generate custom hardware or sequential software. Thethesis uses a digital equalizer to illustrate the concepts andpotential of ForSyDe.</p><p>Electronic System Design, Hardware/Software Co-Design,Electrical Engineering</p>

A case study has been done at Dynapac Compaction Equipment AB in Karlskrona in order to improve the internal flow of the production. The “Supermarket Storage”, an adjoining storage that feed material to the lean production in the “Z-line” assembly line with the help of kitting, was chosen to be focused during the optimization of the internal flow. Also, due to the little academic research about kitting it was decided to focus the research on the kitting process and identify how to optimize it. The purpose of the research is to determine optimization methods of a kitting process and fill in the gap in the subject field about kitting optimization. Given the research time limit, the focus was only on the kitting process in the Supermarket Storage and no optimization could change the storage’s layout. This resulted in three research question that will be investigated in the thesis.  Which common approaches exist when it comes to optimizing a kitting process?  What is the result of each optimizing method in the time aspect?  When should an optimization method be used, compared to the other methods that will be tested in this research? In order to solve these questions, was a needfinding process used in order to identify the kitting process current problems and the needs of the employees. With this, three optimization methods were identified and selected to be used to optimize the kitting process; optimization of routing, optimization of family grouping and optimization of an electronic system. The optimization of routing focused on the route that the kitters travel and the optimization of the family grouping focused on the article distribution in the Supermarket Storage; there each kitting operation’s articles should be stored in the same zone. Finally, the optimization of the electronic system, investigated the possibility to utilize a pick to scan system with the kitting process. Each optimization was implemented in different field experiment in order to identify how each optimization affected the kitting process. This resulted in that each optimization had improved the kitting process time efficiency and the electronic system had the biggest impact. Some other results were also observed during the experiments. The route optimization improved the learning curve of the kitting process and the family grouping optimization decreased the bottlenecks in kitting process. The electronic system optimization also implemented new benefits that resulted in a profit 2.5 times the cost of the system. Some of the benefits include removal of unneeded processes, quality control of the kitting process and statistics gathering that can be used to improve the process in the future. These results imply that all three optimization methods can be used in order to improve the time efficiency of a kitting process in a similar storage layout. The routing optimization should be used in a kitting operation with a high rotation of new kitters. The family grouping should be used in a kiting process with bottlenecks in the process and low organization of the article distribution. Ultimately, the electronic system optimization should be used in a kitting process that has unneeded processes and has the need of new tools that the electronic system can implement.

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing. This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient. The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering. The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time. The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function. The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches. Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.

[pt] Compostos férmions pesados se distinguem dos metais típicos em baixas temperaturas, onde fenômenos decorrentes da alta correlação entre os elétrons de condução e os elétrons f dos íons da rede se tornam evidentes. Fatores como uma massa eletrônica efetiva centenas de vezes maior que a massa do elétron livre e a coexistência de ordem magnética com um estado supercondutor atraem interesse crescente para estes materiais. A aplicação de pressão torna possível sintonizar a temperatura de transição antiferromagnética em alguns destes compostos até o zero absoluto, onde flutuações qüânticas se tornam relevantes e, dependendo do composto, um estado supercondutor não convencional pode se manifestar. Neste trabalho, resultados de medidas de resistência elétrica sob pressão realizadas nos compostos Ce2Rh1&#8722;xIrxIn8 são apresentados em diagramas de fases do tipo pressão-temperatura para cada valor de x estudado, e em diagramas do tipo composição- temperatura para algumas pressões representativas. Duas fases supercondutoras são identificadas nos compostos, uma delas induzida, e a outra suprimida pela pressão aplicada. A primeira das fases parece estar relacionada com flutuações magnéticas, enquanto a origem da segunda pode estar relacionada com flutuações de valência. Outras características interessantes podem ser observadas nos diagramas obtidos, como uma possível fase supercondutora reentrante em x = 0.25 e a brusca supressão de supercondutividade em valores de x maiores que 0,8. / [en] Heavy fermion compounds behave differently from typical metals at low temperatures, where the phenomena that arise due to the correlation between conduction electrons and the f ions of the lattice become evident. An increased effective electronic mass that can reach values as high as hundreds of times the free electron mass and the coexistence of magnetic order with a superconducting state attract growing interest to these materials. When external pressure is applied on some of those systems, the antiferromagnetic transition temperature can be tuned towards absolute zero, where quantum critical fluctuations become relevant and, depending on the compound studied, an unconventional superconducting state can manifest itself. In this work, measurements of electrical resistance were made on the compounds Ce2Rh1&#8722;xIrxIn8 and the results were expressed as pressure-temperature phase diagrams for each value of x studied. Temperature-composition phase diagrams for representative pressures were also built. Two superconducting phases can be identified on the Ce2Rh1&#8722;xIrxIn8 system, one of them induced and the other supressed by applied pressure. The first one seems to be related to magnetic spin fluctuations while the second one can be related to valence fluctuations. Other interesting features can be observed on the obtained diagrams, like a possible reentrant superconducting phase at x = 0.25 and the abrupt supression of supercunductivity on values above x = 0.8.

Made available in DSpace on 2015-04-22T22:07:31Z (GMT). No. of bitstreams: 1 Otoniel da Cunha Mendes.pdf: 861096 bytes, checksum: f9b0b1f5cbcbb43097be4c0845d285e1 (MD5) Previous issue date: 2008-01-10 / Conselho Nacional de Desenvolvimento Científico e Tecnológico / In this work we will investigate the space structure and the dispersion relations of the collective excitations chiral of low frequency that propagate along the edges of a gas of electrons quasi-one-dimensional (GEQ1D) or quantum wire (CF), subject to an intensive field magnetic normal B, known as magnetoplasmons edge (MPB s). Such MPB s, which properties are implicitly connected to the interaction electron-electron of the states of edge, there are investigated inside the Regime Quantum Hall (RHQI) in the lowest level of Landau, n = 0, in samples of heteroestruturas semidrivers based on GaAs, on temperatures not low-greatly, ~ωc À kB T À ~v(e) gn /2􀁣0. Besides, so that the basic paper of the interaction electron-electron can be observed, the use of a gate (a layer of air) to a distance d of the electronic channel is made necessary, in what there must be clear the observation of an armor-plating (strengthening) of the interaction electron-electron. It is possible to say, in the abridged form, which this study bases on a combination of the equations of the density of current linearizada, Poisson and continuity, in such a way that the equations that govern the collective behaviour of the electrons in a narrow electronic channel can be described in the RHQI. In this case, the choice of the profile of density of load (for temperatures not low-great) is shown of basic importance, permetindo analytical getting the resistividades Hall associated to the density of current. So, as soon as the RHQI was maintained for n = 0, we can determine the equations that describe so much the specter of frequency as for space structure of the MPB s. In this form, such a study also complements previous studies as to the MPB s, in individual, when this one spreads the investicações out on the MPB s obtained in extensive electronic channels (Balev et al., 2000 and of that Silva, 2004) for narrow electronic channels. Finally, such equations are computed numerically through programs (developed in FORTRAN and MAPLE) and analysed by graphic way. / Neste trabalho nós investigaremos a estrutura espacial e as relações de dispersão das excitações coletivas quirais de baixa frequência que se propagam ao longo das bordas de um gás de elétrons quasi-unidimensionais (GEQ1D), ou fio quântico(FQ), sujeito a um intenso campo magnético normal B, conhecidas como magnetoplasmons de borda (MPB s). Tais MPB s, cujas as propriedades estão implicitamente relacionadas à interação elétronelétron dos estados de borda, são investigados dentro do Regime Hall Quântico (RHQI) no mais baixo nível de Landau, n = 0, em amostras de heteroestruturas semicondutoras baseadas em GaAs, em temperaturas não-muito-baixas, ~ωc À kB T À ~v(e) gn /2􀁣0. Além disso, para que o papel fundamental da interação elétron-elétron possa ser observado, a utilização de um portão (uma camada de ar) a uma distância d do canal eletrônico se faz necessário, em que deve ser clara a observação de uma blindagem (fortalecimento) da interação elétron-elétron. Pode-se dizer, de forma resumida, que este estudo se baseia numa combinação das equações da densidade de corrente linearizada, Poisson e continuidade, de tal forma que as equações que regem o comportamento coletivo dos elétrons num estreito canal eletrônico possam ser descritas no RHQI. Neste caso, a escolha do perfil de densidade de carga (para temperaturas não-muito-baixas) se mostra de fundamental importância, permetindo a obtenção analítica das resistividades Hall associada à densidade de corrente. Assim, uma vez mantido o RHQI para n = 0, podemos determinar as equações que descrevem tanto o espectro de freqüência quanto a estrutura espacial dos MPB s. Dessa forma, tal estudo também complementa estudos anteriores a respeito dos MPB s, em particular, quando este estende as investicações sobre os MPB s obtidos em extensos canais eletrônicos (Balev et al., 2000 e da Silva, 2004) para estreitos canais eletrônicos. Por fim, tais equações são computadas numericamente por meio de programas (desenvolvidos em FORTRAN e MAPLE) e analisadas por meio gráfico.

<p>The electronic system of a modern vehicle is essential to achieve a successful automotive product. Vehicle development is performed by integrating components that include embedded electronics from several suppliers.</p><p>This thesis present results on the subject of integration of automotive electronic systems. Our studies aim at providing knowledge on how to integrate automotive electronic systems successfully in a setting where vehicles are developed based on existing platforms. We focus on early phases of automotive electronic system development and in particular on the decisions taken in integration of electronic sub-systems. The contribution is the presented support for making decisions to successfully integrate electronic systems for modern vehicles. The contribution includes an overview of driving factors of automotive electronics system design, a validated set of success practices for the integration of electronic components, and the proposal and demonstration of a decision model. The influential factors and the validated set of practices stems from case studies of products and projects while the proposed decision model is a result of combining two general models for architecture analysis and decision making, ATAM and AHP.</p><p>We demonstrate that choices in strategy and design preceding integration are central to achieve a successful integration. Our studies show that problems arise from omitted strategy decisions and we provide a checklist for decision making in the areas; functionality, platform, integration design, and assigning responsibilities. We provide a recommendation that we validate in a multiple cases study where fulfillment of recommendations is demonstrated to affect project success in integration projects.</p><p>The potential gain for OEMs using our results lies in achieving more solid foundations for design decisions. Designers and managers could potentially find central decisions on integration strategy early that, if omitted, could cause delays. Thus, applying the result could avoid pitfalls and enable successful integration projects.</p>

In this thesis, vibration analyses of electronic assemblies that consist of an electronic box, printed circuit board and electronic components are presented. A detailed vibration analysis of a real electronic assembly is performed by finite element methods and vibration tests. Effects of component addition and component modeling are investigated by finite element analysis in detail. Results are compared in order to identify the most efficient, reliable and suitable method depending on the type of problem. Experimental results for the vibration of an electronic box, PCB and components are presented and discussed. Furthermore, an analytical model that represents a printed circuit board and electronic component is suggested for fixed and simply supported boundary conditions of the PCB. Different types of electronic components are modeled analytically to observe different dynamic characteristics. The validity of the analytical model is computationally checked by comparing results with those of finite element solution.