The electronic system of a modern vehicle is essential to achieve a successful automotive product. Vehicle development is performed by integrating components that include embedded electronics from several suppliers. This thesis present results on the subject of integration of automotive electronic systems. Our studies aim at providing knowledge on how to integrate automotive electronic systems successfully in a setting where vehicles are developed based on existing platforms. We focus on early phases of automotive electronic system development and in particular on the decisions taken in integration of electronic sub-systems. The contribution is the presented support for making decisions to successfully integrate electronic systems for modern vehicles. The contribution includes an overview of driving factors of automotive electronics system design, a validated set of success practices for the integration of electronic components, and the proposal and demonstration of a decision model. The influential factors and the validated set of practices stems from case studies of products and projects while the proposed decision model is a result of combining two general models for architecture analysis and decision making, ATAM and AHP. We demonstrate that choices in strategy and design preceding integration are central to achieve a successful integration. Our studies show that problems arise from omitted strategy decisions and we provide a checklist for decision making in the areas; functionality, platform, integration design, and assigning responsibilities. We provide a recommendation that we validate in a multiple cases study where fulfillment of recommendations is demonstrated to affect project success in integration projects. The potential gain for OEMs using our results lies in achieving more solid foundations for design decisions. Designers and managers could potentially find central decisions on integration strategy early that, if omitted, could cause delays. Thus, applying the result could avoid pitfalls and enable successful integration projects.

Magister Commercii (Information Management) - MCom(IM) / In South Africa, public health facilities provide free antiretroviral treatment (ART) mainly via primary healthcare (PHC) nurses. To streamline data collection an electronic HIV information system (TIER.Net), was introduced in 2010. Data originates in paper-based records completed by clinicians with the data from these paper systems then being captured into TIER.Net by clerical data capturers. TIER.Net is designed to effectively monitor outcomes of the ART programme and generate information for planning, management and decision making. For Enock Mgijima subdistrict to attain these functions, it is imperative that data collected at the 21 PHC facilities in the sub-district be of good quality. There has been uncertainty around the quality levels of the data collected through the paper records and TIER.Net, and it was unclear which factors promote or inhibit improved data quality.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第20815号 / 工博第4419号 / 新制||工||1687(附属図書館) / 京都大学大学院工学研究科分子工学専攻 / (主査)教授 関 修平, 教授 佐藤 啓文, 教授 梶 弘典 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

[pt] Este trabalho, relacionado com a área de modelagem de cargas para estudos de estabilidade transitória de sistemas elétricos, tem por objetivo discutir a adequação dos modelos clássicos normalmente utilizados, bem como o aprimoramento e desenvolvimento de representações para cargas com características específicas. Inicialmente, são enfocados os aspectos das representações clássicas de cargas e, através de desenvolvimentos teóricos e estudos computacionais, ressaltadas as adequações destas estratégias ao contexto atual. Reconhecendo algumas limitações quanto às técnicas para a obtenção dos parâmetros de motores de indução, apresenta- se procedimentos sistematizados para o tratamento destes componentes de carga. Tendo em vista a busca da melhoria de modelos e respostas aos questionamentos a respeito da relevância da inclusão dos efeitos da variação da freqüência sobre as cargas e parâmetros da rede, o trabalho prossegue com investigações nesta direção. Objetivando a análise do desempenho dos modelos simplificados de cargas através de funções algébricas, são discutidas as propostas atuais e verificadas suas adequações aos estudos de estabilidade. Finalmente, considerando a importância atual das cargas conversoras estáticas, são desenvolvidos modelos apropriados e realizados os estudos necessários à incorporação de unidades retificadoras em programas de estabilidade. / [en] This work, involved with the load modeling for electrical system transiente stability analysis, aim to discuss the classical load models normally used, and to develop and improve representations of specific types of loads. Initially, aspects concerned with classical load representations are dealt with aiming to evaluate, through theoretical and computational analyses, the current employment of such models. Knowing that the techiques to obtain induction motor parameters are still deficient, this work presents some systematic procedures for the treatment of such loads. Additionally, it continues seeking improvements in electrical system component models and answers to the questions about the need for inclusion of the frequency variation effects on loads and network parameters. Moreover, it takes into account the tendencies of using simplified load models represented by algebraic expressions. Some recent proposals in this area are discussed and tested with a view to acess the perfomance of the models in stability studies. Finally, considering the present importance of static load converters, it is developed the related models and presented the necessary studies to include rectifier units in stability programs.

No description available.

Investir na capacidade de identificação dos diferentes níveis de desempenho dos servidores de uma Instituição é uma das mais importantes práticas da gestão de recursos humanos na atualidade. O empregador busca caracterizar os diferentes níveis de desempenho e utiliza esta informação da maneira construtiva visando à melhoria de processos e resultados para a Instituição. A avaliação regular de desempenho é uma das formas de identificar e valorizar as boas práticas que se alinham com a missão e valores da Instituição, e prover devolutiva para corrigir rumos e fazer ajustes necessários. Existem várias formas de se fazer avaliação de desempenho dos membros de uma equipe de trabalho, entretanto a tendência tem sido a utilização de sistemas informatizados que aumentam a capacidade de gerenciamento dos dados coletados, controle e feedback das avaliações aos servidores. Recentemente implantou-se o Sistema Eletrônico de Avaliação de Desempenho (SEAD) para os servidores da área médica, no Hospital das Clínicas da Faculdade de Medicina de Ribeirão Preto da Universidade de São Paulo (HCFMRP-USP), com o intuito de atender a Lei Complementar 1193/2013, que exige a avaliação de desempenho dos médicos do Estado de São Paulo para fins de pagamento do Prêmio de Produtividade Médica (PPM). O objetivo é descrever e caracterizar o SEAD, além de avaliar os resultados dos primeiros anos de sua implementação. Caracteriza-se como um estudo descritivo na parte inicial, onde foram apresentadas todas as etapas de planejamento e implementação do SEAD para avaliação dos médicos do HCFMRP-USP, inclusive com as principais diferenças entre o novo sistema e o sistema manual que havia previamente. Na etapa seguinte, de implementação, caracteriza-se por um estudo do tipo \"pesquisaação\" com duração de três anos em que diversos ajustes foram feitos a partir do que foi aprendido nas avaliações iniciais do próprio sistema. Na etapa final foram feitas entrevistas com os docentes avaliadores dos serviços com o maior número de médicos do HCRP. Este estudo foi aprovado pelo Comitê de Ética do HCRP. Dentre os resultados do estudo apresentaremos uma descrição detalhada do SEAD aplicado na área médica e as diferenças observadas em relação aos sistemas de avaliação anteriormente utilizados pelo HCRP. Diversas informações e indicadores foram obtidos em tempo real e disponibilidados para gestores médicos e a adminstração de recursos humanos do HCFMRP, tais como: o número de servidores avaliados, os avaliadores que realizaram as avaliações ou os avaliadores que não realizaram as avaliações, a quantidade de servidores avaliados por cada avaliador, quem foi avaliado, a nota obtida e o percentual de recebimento do PPM que cada médico do hospital recebeu. Os resultados dos primeiros anos de utilização e as melhorias que foram feitas no SEAD também estão descritas nos resultados deste estudo. A percepção dos avaliadores e usuários do sistema é de que o SEAD representou ganhos em termos de armazenamento de dados, acesso à informação para a tomada de decisões e principalmente por propiciar o direcionamento das políticas de incentivo aos médicos do HCRP alinhada com os interesses da própria instituição. De um modo geral os avaliadores que participaram voluntariamente do estudo avaliaram o SEAD de maneira bastante positiva. A avaliação de pessoal para fins de promoção ou premiação é sempre um desafio do ponto de vista pessoal e a disponibilidade de recursos que aumentam a transparência e promovem equidade com agilidade e simplicidade são extremamente importantes, especialmente para as organizações públicas. / Investing in the ability to identify the different levels of performance of an institution\'s servers is one of the most important human resources management practices today. The employer seeks to characterize the different levels of performance and uses this information in a constructive way aiming at improving processes and results for the Institution. Regular performance evaluation is one way to identify and value good practices that align with the Institution\'s mission and values, and to provide feedback to correct directions and make necessary adjustments. There are several ways to evaluate the performance of members of a work team. However, the tendency has been to use computerized systems that increase the capacity to manage the data collected, control and feedback of the evaluations to the servers. Recently the Electronic Performance Evaluation System (SEAD) was implanted for the medical staff, at the Hospital das Clínicas of the Medical School of Ribeirão Preto of the University of São Paulo (HCFMRP-USP), in order to comply with the Law Complementary Act 1193/2013, which requires the performance evaluation of physicians of the State of São Paulo for the purpose of payment of the Medical Productivity Award (PPM). The objective is to describe and characterize the SEAD, besides evaluating the results of the first years of its implementation. It is characterized as a descriptive study in the initial part, where all the SEAD planning and implementation steps for the evaluation of HCFMRP-USP physicians were presented, including the main differences between the new system and the manual system that had previously been presented. In the next stage of implementation, it is characterized by a three-year \"action-research\" study in which several adjustments were made based on what was learned in the initial evaluations of the system itself. In the final stage interviews were made with the teachers evaluating the services with the largest number of HCRP physicians. This study was approved by the HCRP Ethics Committee. Among the results of the study we will present a detailed description of the SEAD applied in the medical area and the differences observed in relation to the evaluation systems previously used by the HCRP. Various information and indicators were obtained in real time and available to HCFMRP medical managers and human resources management, such as: the number of evaluated servers, the evaluators who carried out the evaluations or the evaluators who did not carry out the evaluations, the amount of servers evaluated by each evaluator, who was evaluated, the grade obtained and the percentage of receipt of PPM that each hospital doctor received. The results of the first years of use and the improvements that have been made in SEAD are also described in the results of this study. The perception of the evaluators and users of the system is that the SEAD represented gains in terms of data storage, access to information for decision-making and, above all, to foster the orientation of policies to encourage HCRP physicians in line with the interests of the system itself institution. In general, evaluators who voluntarily participated in the study evaluated SEAD in a very positive way. Evaluating staff for promotion or reward is always a challenge from a personal standpoint, and the availability of resources that increase transparency and promote equity with agility and simplicity are extremely important, especially for public organizations.

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing. This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient. The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering. The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time. The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function. The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches. Finally we present two publications that resulted from the many detours we have taken along the winding path of our research. / QC 20100909

In this thesis, I present a microscopic theory of quantum circuits based on interacting electron spins in quantum dot molecules. We use the Linear Combination of Harmonic Orbitals-Configuration Interaction (LCHO-CI) formalism for microscopic calculations. We then derive effective Hubbard, t-J, and Heisenberg models. These models are used to predict the electronic, spin and transport properties of a triple quantum dot molecule (TQDM) as a function of topology, gate configuration, bias and magnetic field. With these theoretical tools and fully characterized TQDMs, we propose the following applications: 1. Voltage tunable qubit encoded in the chiral states of a half-filled TQDM. We show how to perform single qubit operations by pulsing voltages. We propose the "chirality-to-charge" conversion as the measurement scheme and demonstrate the robustness of the chirality-encoded qubit due to charge fluctuations. We derive an effective qubit-qubit Hamiltonian and demonstrate the two-qubit gate. This provides all the necessary operations for a quantum computer built with chirality-encoded qubits. 2. Berry's phase. We explore the prospect of geometric quantum computing with chirality-encoded qubit. We construct a Herzberg circuit in the voltage space and show the accumulation of Berry's phase. 3. Macroscopic quantum states on a semiconductor chip. We consider a linear chain of TQDMs, each with 4 electrons, obtained by nanostructuring a metallic gate in a field effect transistor. We theoretically show that the low energy spectrum of the chain maps onto that of a spin-1 chain. Hence, we show that macroscopic quantum states, protected by a Haldane gap from the continuum, emerge. In order to minimize decoherence of electron spin qubits, we consider using electron spins in the p orbitals of the valence band (valence holes) as qubits. We develop a theory of valence hole qubit within the 4-band k.p model. We show that static magnetic fields can be used to perform single qubit operations. We also show that the qubit-qubit interactions are sensitive to the geometry of a quantum dot network. For vertical qubit arrays, we predict that there exists an optimal qubit separation suitable for the voltage control of qubit-qubit interactions.

In this thesis, I present a microscopic theory of quantum circuits based on interacting electron spins in quantum dot molecules. We use the Linear Combination of Harmonic Orbitals-Configuration Interaction (LCHO-CI) formalism for microscopic calculations. We then derive effective Hubbard, t-J, and Heisenberg models. These models are used to predict the electronic, spin and transport properties of a triple quantum dot molecule (TQDM) as a function of topology, gate configuration, bias and magnetic field. With these theoretical tools and fully characterized TQDMs, we propose the following applications: 1. Voltage tunable qubit encoded in the chiral states of a half-filled TQDM. We show how to perform single qubit operations by pulsing voltages. We propose the "chirality-to-charge" conversion as the measurement scheme and demonstrate the robustness of the chirality-encoded qubit due to charge fluctuations. We derive an effective qubit-qubit Hamiltonian and demonstrate the two-qubit gate. This provides all the necessary operations for a quantum computer built with chirality-encoded qubits. 2. Berry's phase. We explore the prospect of geometric quantum computing with chirality-encoded qubit. We construct a Herzberg circuit in the voltage space and show the accumulation of Berry's phase. 3. Macroscopic quantum states on a semiconductor chip. We consider a linear chain of TQDMs, each with 4 electrons, obtained by nanostructuring a metallic gate in a field effect transistor. We theoretically show that the low energy spectrum of the chain maps onto that of a spin-1 chain. Hence, we show that macroscopic quantum states, protected by a Haldane gap from the continuum, emerge. In order to minimize decoherence of electron spin qubits, we consider using electron spins in the p orbitals of the valence band (valence holes) as qubits. We develop a theory of valence hole qubit within the 4-band k.p model. We show that static magnetic fields can be used to perform single qubit operations. We also show that the qubit-qubit interactions are sensitive to the geometry of a quantum dot network. For vertical qubit arrays, we predict that there exists an optimal qubit separation suitable for the voltage control of qubit-qubit interactions.

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry. / Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria. / Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria.