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The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is primarily aimed at providing increased physical test access to surface mounted devices on printed circuit boards (PCB). Using boundary scan avoids using functional testing and In-circuit-techniques like 'bed of nails' for structurally testing PCBs as increasing densities and complexities made opting for them a herculean task. Though the standard has had a revolutionizing effect on board testing conducted during the development and production phases, there is a lack of a standardized mechanism to allow IEEE 1149.1 to be used in a system post installation. This has led to problems typically encountered during field test runs, like the issue of high number of No-Fault-Found (NFF), being left unaddressed. The solution lies in conducting a structural test after a given module has already been installed in the system. This can be done by embedding the programmability features of the boundary scan test mechanism into the Unit under test (UUT) thereby enabling the UUT to conduct boundary scan based self tests without the need of external stimuli. In this thesis, a test and debug framework, which aims to use boundary-scan in post system-installation, is the subject of a study and subsequent enhancement. The framework allows embedding much of the test vector deployment and debug mechanism onto the Unit under test (UUT) to enable its remote testing and debug. The framework mainly consists of a prototype board which, along with the UUT, comprise the 'embedded system'. The following document is a description of the phased development of above said framework and its intended usage in the field.

Modern embedded systems are evolving in the direction of increased adaptivity and complexity. It is extremely important for a system with limited resource to be adaptive in order to maximize its efficiency of resource usage while guaranteeing a high level of fault tolerance and QoS. This report aims at exploring such a kind of system, i.e. Adaptive Embedded System (AES), which is featured by dynamic reconfiguration at runtime. Based on the investigation and analysis of a variety of case studies related with AES, we proposed the conceptual view and overall architecture of an AES by highlighting its predominant characteristics. We also made an incomplete but detailed summary of the most popular techniques that can be used to realize adaptivity. Those techniques are categorized into dynamic CPU/network resource re-allocation and adaptive fault tolerance. A majority of adaptive applications resort to one or more of those techniques. Besides, there is a separate discussion on dynamic reconfiguration and mode switch for AES. Finally, we classify adaptivity into different modeling problems at a higher abstraction level and build UPPAAL models for two different AESs, a smart phone and an object-tracking robot. Our UPPAAL models provide clear demonstration on how a typical AES works.

Speech recognition has been an important area of research during the past decades. The usage of automatic speech recognition systems is rapidly increasing among different areas, such as mobile telephony, automotive, healthcare, robotics and more. However, despite the existence of many speech recognition systems, most of them use platform specific and non-publicly available software. Nevertheless, it is possible to develop speech recognition systems using already existing open source technology. The aim of this master's thesis is to develop an interactive and speaker independent speech recognition system. The system shall be able to identify predetermined keywords from incoming live speech and in response, play audio files with related information. Moreover, the system shall be able to provide a response even if no keyword was identified. For this project, the system was implemented using PocketSphinx, a speech recognition library, part of the open source Sphinx technology by the Carnegie Mellon University. During the implementation of this project, the automation of different steps of the process, was a key factor for a successful completion. This automation consisted on the development of different tools for the creation of the language model and the dictionary, two important components of the system. Similarly, the audio files to be played after identifying a keyword, as well as the evaluation of the system's performance, were fully automated. The tests run show encouraging results and demonstrate that the system is a feasible solution that could be implemented and tested in a real embedded application. Despite the good results, possible improvements can be implemented, such as the creation of a different phonetic dictionary to support different languages.

This thesis presents a systematic and structured way to migrate embedded software running on a digital signal processor to a different hardware platform. The solution includes using design patterns, a layered architecture and clearly defined interfaces to perform hardware abstraction. The proposed solution is aimed for a particular embedded system used in a product at AI.

Actiwave AB delivers audio solutions for active speakers. One of the features is that audio can be streamed to the speakers over a local network connection. The module that provides this functionality is expensive. This thesis investigates if this can instead be achieved by taking advantage of the Spartan-6 FPGA on their platform, using part of it as a MicroBlaze soft processor on which a rendering device can be implemented. The thesis discusses design decisions such as selection and integration of operating system, UPnP framework and media decoder. A fully functional prototype application for a desktop computer was implemented, with the intention of porting it to the FPGA platform. There turned out to be too many compability issues though, so instead, a simpler renderer was implemented on the FPGA. Mp3 music files were successfully streamed to and decoded on the soft processor, but without fulfilling real-time constraints. The conclusion is that it is reasonable to implement a UPnP Media Renderer on the FPGA. Decoding in real-time can be an issue due to insufficient performance of the soft processor, but several possible solutions exist.

The number of electronic control units in heavy-duty vehicles has grown dramatically overthe last few decades. This has led to the use of communication buses to reduce the complexityand weight of the networks. There are reasons to believe that the de facto standardcommunication interface in the automotive industry, the Controller Area Network, is obsoletein some areas. Hence an evaluation of available communication interfaces is needed.This study focuses on lower levels of the Open Systems Interconnect (osi) model. Initially atheoretical study is presented in order to give an overview of automotive embedded systemsin general and different communication interfaces in particular. Ethernet and FlexRay areidentified as two interfaces of interest for future use in Scanias vehicles. The former is new inautomotive applications but is believed to become popular over the years to come. A possibleuse of this interface could be as a backbone to take the load off other interfaces. The use ofFlexRay in Scanias vehicles is limited because of the modular system used and the staticscheduling needed. It could however be used between mandatory ecus where the nodes andthe messages are all known beforehand.The report also contains the result from emission measurements on a number of interfacesperformed using a stripline antenna in a shielded enclosure. Strong conclusions can not bedrawn since it’s hard to tell what the transceivers, circuit boards and interfaces contributedto in the spectra with the method used. The FlexRay hardware is worse than for the otherinterfaces. Similarities can be seen between low-speed and high-speed can but it could becharacteristics of the transceivers used rather than the interface itself.

The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. While classical memory tests cover the static faults, they are not sufficient to cover dynamic faults which have emerged in VDSM technologies. The purpose of this thesis is implementation of a memory BIST that targets static faults as well as dynamic faults while maintaining an acceptable test time and area overhead.At first, and as a semester project, the functional fault models (FFMs) associated with state-of-the-art SRAM technologies have been studied and state-of-the-art memory testing algorithms, targeting these FFMs have been presented.Next, and as part of this master's thesis, a combination of March LR and March AB memory testing algorithms is selected and modified to support testing word-oriented memories. Furthermore, this algorithm is extended to provide support for detecting Data-Retention Faults. This algorithm is then implemented using Verilog HDL in Register-Transfer Level of abstraction.The implemented MemBIST is then evaluated with respect to area, performance and fault coverage. A bit-oriented March LR-based MemBIST, currently in use on Atmel® AVR® micro-controllers, is used as a reference for benchmarking purposes. All target fault primitives (FPs) have been implemented using behavioral Verilog HDL and simulated with both MemBISTs.Our evaluations show that our word-oriented MemBIST can provide a 500% performance advantage (due to the word-oriented execution) for 32-bit memories and at the same time has a better fault coverage compared to the reference MemBIST. The implemented algorithm can detect all static and realistic dynamic inter-word memory faults as well as most static and realistic dynamic intra-word faults. The implemented MemBIST also maintains a very small area overhead due to sharing the required registers with existing system components.Keywords: MemBIST, Built-In Self Test, Memory Testing, March Test, Fault Model, Fault Coverage, Fault Detection

This dissertation describes the fabrication and integration of a thin film edge emitting laser (EEL) whose optical output is coupled into a polymer waveguide integrated onto the same electrical interconnection substrate. This embedded laser/waveguide structure is a fundamental building block toward the realization of planar lightwave circuits using embedded optical interconnections. The demonstration of a thin film laser integrated with a planar waveguide eliminates the need for either an external optical source coupled to the waveguide or a bump bonded optical source with a beam turning element to turn an optical beam into the waveguide. In this work, the wedge-induced facet cleaving (WFC) method is adapted to fabricate the thin film EELs. Bisbenzocyclobutene (BCB) polymers are used to fabricate channel waveguides, and thin film lasers are integrated with the polymer waveguides. The coupling efficiency from the laser to the polymer waveguide is estimated through measurement and theoretically calculated. In the theoretical calculation, the thin film transfer matrix method is used to analyze the optical modes in the semiconductor cavity. The coupling efficiency from the laser to the polymer waveguide is analyzed using a finite element method (FEM), and are then compared to the experimental results. The experimentally estimated coupling efficiency is in good agreement with that of the theoretical calculation. In addition, the relationship between threshold current, output power, and facet reflectivity of the thin film laser is analyzed using FEM.

Multilayer embedded passives (resistors, inductors, and capacitors) on a printed wiring board can help to meet high performance requirements at a low cost and at a smaller size. Such an integration of embedded passives has new challenges with respect to design, materials, manufacturing, thermal management and reliability. As the area of integral passives on printed circuit boards is relatively new, there is inadequate literature on the thermo-mechanical reliability of integral passives. Therefore, there is a compelling need to understand the thermo-mechanical reliability of integral passives through the development of physics-based models as well as through experiments, and this thesis aims to develop such an experimental and theoretical program to study the thermo-mechanical reliability of integral passives.. As integral passives are often composite layers with dissimilar material properties compared to the other layers in the integral substrate, it is essential to ensure that RLC characteristics of the embedded passives do not deteriorate with thermal cycling due to thermo-mechanical deformations. This thesis aims to study the changes in the passive characteristics due to the thermally-induced deformations. Embedded capacitors and inductors have been looked at specifically in this research. Multi-field physics-based models have been constructed to determine the change in electrical parameters after thermal cycling. The thermo-mechanical models assume direction-dependent material properties for the board substrate and interconnect copper layers and temperature-dependent properties for interlayer dielectric and passive layers. Using the deformed geometry, the electrical characteristics have been determined at low frequency. In parallel to the models, test vehicle substrates have been subjected to 1000 thermal cycles between -55??o 125??nd high humidity and temperature conditions at 85??5RH for 500 hours, and it has been observed that there are significant changes in the electrical parameters. The results obtained from the physics-based simulations have been validated against the measured electrical characteristics from the fabricated functional test boards that have been thermal cycled.