The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in current embedded processors. Multi-core processors represent a good design solution to cope with such higher performance requirements due to their better performance-per-watt ratio while maintaining the core design simple. Moreover, multi-cores also allow executing mixed-criticality level workloads composed of tasks with and without hard real-time requirements, maximizing the utilization of the hardware resources while guaranteeing low cost and low power consumption. Despite those benefits, current multi-core processors are less analyzable than single-core ones due to the interferences between different tasks when accessing hardware shared resources. As a result, estimating a meaningful Worst-Case Execution Time (WCET) estimation - i.e. to compute an upper bound of the application's execution time - becomes extremely difficult, if not even impossible, because the execution time of a task may change depending on the other threads running at the same time. This makes the WCET of a task dependent on the set of inter-task interferences introduced by the co-running tasks. Providing a WCET estimation independent from the other tasks (time composability property) is a key requirement in hard real-time systems. This thesis proposes a new multi-core processor design in which time composability is achieved, hence enabling the use of multi-cores in hard real-time systems. With our proposals the WCET estimation of a HRT is independent from the other co-running tasks. To that end, we design a multi-core processor in which the maximum delay a request from a Hard Real-time Task (HRT), accessing a hardware shared resource can suffer due to other tasks is bounded: our processor guarantees that a request to a shared resource cannot be delayed longer than a given Upper Bound Delay (UBD). In addition, the UBD allows identifying the impact that different processor configurations may have on the WCET by determining the sensitivity of a HRT to different resource allocations. This thesis proposes an off-line task allocation algorithm (called IA3: Interference-Aware Allocation Algorithm), that allocates tasks in a task set based on the HRT's sensitivity to different resource allocations. As a result the hardware shared resources used by HRTs are minimized, by allowing Non Hard Real-time Tasks (NHRTs) to use the rest of resources. Overall, our proposals provide analyzability for the HRTs allowing NHRTs to be executed into the same chip without any effect on the HRTs. The previous first two proposals of this thesis focused on supporting the execution of multi-programmed workloads with mixed-criticality levels (composed of HRTs and NHRTs). Higher performance could be achieved by implementing multi-threaded applications. As a first step towards supporting hard real-time parallel applications, this thesis proposes a new hardware/software approach to guarantee a predictable execution of software pipelined parallel programs. This thesis also investigates a solution to verify the timing correctness of HRTs without requiring any modification in the core design: we design a hardware unit which is interfaced with the processor and integrated into a functional-safety aware methodology. This unit monitors the execution time of a block of instructions and it detects if it exceeds the WCET. Concretely, we show how to handle timing faults on a real industrial automotive platform. / La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en industrias como la automovilística y la de aviación, está impulsando un incremento en el rendimiento necesario en los actuales procesadores empotrados. Los procesadores multi-núcleo son una solución eficiente para obtener un mayor rendimiento ya que aumentan el rendimiento por vatio, manteniendo el diseño del núcleo simple. Por otra parte, los procesadores multi-núcleo también permiten ejecutar cargas de trabajo con niveles de tiempo real mixtas (formadas por tareas de tiempo real duro y laxo así como tareas sin requerimientos de tiempo real), maximizando así la utilización de los recursos de procesador y garantizando el bajo consumo de energía. Sin embargo, a pesar los beneficios mencionados anteriormente, los actuales procesadores multi-núcleo son menos analizables que los de un solo núcleo debido a las interferencias surgidas cuando múltiples tareas acceden simultáneamente a los recursos compartidos del procesador. Como resultado, la estimación del peor tiempo de ejecución (conocido como WCET) - es decir, una cota superior del tiempo de ejecución de la aplicación - se convierte en extremadamente difícil, si no imposible, porque el tiempo de ejecución de una tarea puede cambiar dependiendo de las otras tareas que se estén ejecutando concurrentemente. Determinar una estimación del WCET independiente de las otras tareas es un requisito clave en los sistemas empotrados de tiempo real duro. Esta tesis propone un nuevo diseño de procesador multi-núcleo en el que el tiempo de ejecución de las tareas se puede componer, lo que permitirá el uso de procesadores multi-núcleo en los sistemas de tiempo real duro. Para ello, diseñamos un procesador multi-núcleo en el que la máxima demora que puede sufrir una petición de una tarea de tiempo real duro (HRT) para acceder a un recurso hardware compartido debido a otras tareas está acotado, tiene un límite superior (UBD). Además, UBD permite identificar el impacto que las diferentes posibles configuraciones del procesador pueden tener en el WCET, mediante la determinación de la sensibilidad en la variación del tiempo de ejecución de diferentes reservas de recursos del procesador. Esta tesis propone un algoritmo estático de reserva de recursos (llamado IA3), que asigna tareas a núcleos en función de dicha sensibilidad. Como resultado los recursos compartidos del procesador usados por tareas HRT se reducen al mínimo, permitiendo que las tareas sin requerimiento de tiempo real (NHRTs) puedas beneficiarse del resto de recursos. Por lo tanto, las propuestas presentadas en esta tesis permiten el análisis del WCET para tareas HRT, permitiendo así mismo la ejecución de tareas NHRTs en el mismo procesador multi-núcleo, sin que estas tengan ningún efecto sobre las tareas HRT. Las propuestas presentadas anteriormente se centran en el soporte a la ejecución de múltiples cargas de trabajo con diferentes niveles de tiempo real (HRT y NHRTs). Sin embargo, un mayor rendimiento puede lograrse mediante la transformación una tarea en múltiples sub-tareas paralelas. Esta tesis propone una nueva técnica, con soporte del procesador y del sistema operativo, que garantiza una ejecución analizable del modelo de ejecución paralela software pipelining. Esta tesis también investiga una solución para verificar la corrección del WCET de HRT sin necesidad de ninguna modificación en el diseño de la base: un nuevo componente externo al procesador se conecta a este sin necesidad de modificarlo. Esta nueva unidad monitorea el tiempo de ejecución de un bloque de instrucciones y detecta si se excede el WCET. Esta unidad permite detectar fallos de sincronización en sistemas de computación utilizados en automóviles.

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Energetic particle (alpha particle, cosmic neutron, etc.) induced single event data upset or soft error has emerged as a key reliability concern in SRAMs in sub-100 nanometre technologies. Low operating voltage, small node capacitance, high packing density, and lack of error masking mechanisms are primarily responsible for the soft error susceptibility of SRAMs. In addition, since SRAM occupies the majority of die area in system-on-chips (SoCs) and microprocessors, different leakage reduction techniques, such as, supply voltage reduction, gated grounding, etc., are applied to SRAMs in order to limit the overall chip leakage. These leakage reduction techniques exponentially increase the soft error rate in SRAMs. The soft error rate is further accentuated by process variations, which are prominent in scaled-down technologies. In this research, we address these concerns and propose techniques to characterize and mitigate soft errors in nanoscale SRAMs. We develop a comprehensive analytical model of the critical charge, which is a key to assessing the soft error susceptibility of SRAMs. The model is based on the dynamic behaviour of the cell and a simple decoupling technique for the non-linearly coupled storage nodes. The model describes the critical charge in terms of NMOS and PMOS transistor parameters, cell supply voltage, and noise current parameters. Consequently, it enables characterizing the spread of critical charge due to process induced variations in these parameters and to manufacturing defects, such as, resistive contacts or vias. In addition, the model can estimate the improvement in critical charge when MIM capacitors are added to the cell in order to improve the soft error robustness. The model is validated by SPICE simulations (90nm CMOS) and radiation test. The critical charge calculated by the model is in good agreement with SPICE simulations with a maximum discrepancy of less than 5%. The soft error rate estimated by the model for low voltage (sub 0.8 V) operations is within 10% of the soft error rate measured in the radiation test. Therefore, the model can serve as a reliable alternative to time consuming SPICE simulations for optimizing the critical charge and hence the soft error rate at the design stage. In order to limit the soft error rate further, we propose an area-efficient multiword based error correction code (MECC) scheme. The MECC scheme combines four 32 bit data words to form a composite 128 bit ECC word and uses an optimized 4-input transmission-gate XOR logic. Thus MECC significantly reduces the area overhead for check-bit storage and the delay penalty for error correction. In addition, MECC interleaves two composite words in a row for limiting cosmic neutron induced multi-bit errors. The ground potentials of the composite words are controlled to minimize leakage power without compromising the read data stability. However, use of composite words involves a unique write operation where one data word is written while other three data words are read to update the check-bits. A power efficient word line signaling technique is developed to facilitate the write operation. A 64 kb SRAM macro with MECC is designed and fabricated in a commercial 90nm CMOS technology. Measurement results show that the SRAM consumes 534 μW at 100 MHz with a data latency of 3.3 ns for a single bit error correction. This translates into 82% per-bit energy saving and 8x speed improvement over recently reported multiword ECC schemes. Accelerated neutron radiation test carried out at TRIUMF in Vancouver confirms that the proposed MECC scheme can correct up to 85% of soft errors.

The purpose of this qualitative action research study was to explore content area teachers’ understanding of literacy, the strategies they use in working with content materials to support their students’ learning of content, and how collaboration with a literacy expert informs literacy instruction. In my work with content area teachers, they have expressed the need for support as they try new literacy strategies when engaging students in content material. Literacy skills are a part of all content areas. Therefore, literacy scholars need an ongoing understanding of how content teachers define and perceive literacy in their content area in order to provide this support. Framed within a sociocultural lens (Vygotsky, 1978), this action research study (Schmuck, 2006) examined how high school content area teachers engaged students in reading content material as they implemented literacy strategies to support students’ access to content. Guiding this study were the following questions: (a) How do content area teachers define and perceive literacy and specifically define literacy in their content area? (b) How do teachers use literacy strategies they learn in professional development sessions? (c) Is there a benefit when a literacy specialist and a content area teacher collaborate to design literacy instruction? Participants in this study included three content area teachers: a math teacher, a business teacher, and English teacher. Data collection occurred throughout the spring term 2012 in the school where the participants work. Data sources included semi-structured interviews, observations, discussions generated from collaborative planning sessions with the researcher, informal debriefings with participants, and a researcher journal. Themes abstracted from the data were (a) teachers’ definitions of literacy did not change over the course of the study, (b) their disposition toward use of strategies did change over the course of the study, and (c) collaborative, embedded professional development between the content area teacher and literacy specialist was an important factor in changing disposition. This action research study emphasizes a need for literacy specialists in schools and embedded, ongoing professional development, and informs literacy specialists how content area teachers can be supported as they engage students in reading content material.

Embedded system plays an important role in various industry applications. An embedded system is consisting of software and hardware. The hardware platform of conventional embedded system is typically based on IC chips that have fixed resources. Besides, with the development of FPGA, an emerging approach for designing embedded system is implementing soft IP cores on FPGAs. Soft IP cores are synthesizable hardware blocks described in HDL language. Their source code can be either open or close to public. For example, OpenRISC 1200, is an open source 32-bit RISC microprocessor. In addition, the increasing complexity of embedded system forces software developers to consider operating system support to reduce their workload. Thus, in this thesis, a prototype of open source IP based embedded system with Linux is implemented on Atlys (Xilinx Spartan-6) FPGA board and the goal is to evaluate if the system is appropriate for industrial applications. The hardware platform is ORPSOC, which is a reference SoC design based on OpenRISC 1200 processor. For software, Linux operating system is installed. Furthermore, an application executes on Linux is developed that reads the output of an I2C compass sensor-LSM303DLM. With the success of the application and the investigation of license issues, the conclusion is drawn that open source IP based embedded system with Linux is usable for industry. Although comparing to conventional embedded system, the open source IP based embedded system with Linux has following cons, such as high product cost, basic-supported development environment and more difficult software development if Linux driver doesn’t support the hardware. However, its pros are high flexibility and scalability, high software portability, low software development difficulty and high reusability that make it more suitable for industry usage.

Many efforts have been carried out to provide transmission reliability in the history of communication systems. As the demand for real-time applications increased, providing a reliable communication in a timely manner for such applications is strongly desired. Considering timing constraints makes the issue of achieving reliability more difficult. This thesis concentrates on providing reliability for real-time communication in embedded networks by achieving a timing analysis and using the ARQ concept. What is carried out in this thesis is providing retransmission in a real-time manner for embedded networks according to application request. The thesis work focuses on one packet retransmission over a point to point link, but the concept is rich and can be extended to cover application request in real-time embedded networks. Two methods have been fulfilled, and a simulation has been done on the timing analysis focusing on the performance in accepting real-time traffic in the form of separate channels for each application request. The protocol combines ARQ and a scheduling algorithm as a base to support retransmission for hard real-time applications in embedded networks.

Exploitation of wireless sensor networks (WSNs) in ubiquitous computing environments is continuously increasing for gathering data. Contemporary distributed software systems on WSNs for pragmatic business applications have become extremely adaptive, dynamic, heterogeneous and large scaled. Management of such system is not trivial to fulfil these features, leading to more and more complex management and configuration. Along with encompassing state of art and novel techniques for such diversely dynamic system, in this thesis two alternative techniques namely “task initiation by command” and “run-time task deployment and processing” are compared, for such system’s setup and configuration. Both techniques have their own pros and cons which makes them suitable according to the requirements and contextual situations. A lot of effort has been put to make WSNs more and more efficient in terms of computations and power consumption. Hence comparative analysis of both techniques used in this report to setup and configure WSN can be a benchmark to lead towards most appropriate solution to compensate the need of efficient energy and resource consumption.Both alternative schemes are implemented to setup WSN on Sun Microsystems sunSPOT (Small Programmable Object Technology) sensor nodes which are embedded microcontrollers and programmed them in java (j2me). It performs radio communication between wireless sensors and host via sink node also called base station, along with over the air run-time management of sensors. SunSPOTs built in libraries and KSN libraries are used to implement these alternatives and compare the memory footprint, communication pattern and energy consumption.Exploitation of wireless sensor networks (WSNs) in ubiquitous computing environments is continuously increasing for gathering data. Contemporary distributed software systems on WSNs for pragmatic business applications have become extremely adaptive, dynamic, heterogeneous and large scaled. Management of such system is not trivial to fulfil these features, leading to more and more complex management and configuration. Along with encompassing state of art and novel techniques for such diversely dynamic system, in this thesis two alternative techniques namely “task initiation by command” and “run-time task deployment and processing” are compared, for such system’s setup and configuration. Both techniques have their own pros and cons which makes them suitable according to the requirements and contextual situations. A lot of effort has been put to make WSNs more and more efficient in terms of computations and power consumption. Hence comparative analysis of both techniques used in this report to setup and configure WSN can be a benchmark to lead towards most appropriate solution to compensate the need of efficient energy and resource consumption.Both alternative schemes are implemented to setup WSN on Sun Microsystems sunSPOT (Small Programmable Object Technology) sensor nodes which are embedded microcontrollers and programmed them in java (j2me). It performs radio communication between wireless sensors and host via sink node also called base station, along with over the air run-time management of sensors. SunSPOTs built in libraries and KSN libraries are used to implement these alternatives and compare the memory footprint, communication pattern and energy consumption.

Electronic systems installed in their operation environments often require regular testing. The nanometer transistor size in new IC design technologies makes the electronic systems more vulnerable to defects. Due to certain reasons like wear out or over heating and difficulty to access systems in remote areas, in-field testing is vital. For in-field testing, embedded test controllers are more effective in terms of maintenance cost than external testers. For in-field testing, fault coverage, high memory requirements, test application time, flexibility and diagnosis are the main challenges. In this thesis, an Embedded Test Controller (ETC) is designed and implemented which provides flexible in-field testing and diagnostic capability with high fault coverage. The ETC has relatively low memory requirements for storing deterministic test data as compared to storing complete test vectors. The test patterns used by the ETC are stored separately for each component of the device under test, in system memory. The test patterns for each component are concatenated during test application according to a flexible test command. To address test application time (which corresponds to down time of the system), two different versions of the ETC are designed and implemented. These versions provide a trade off between test application time and hardware overhead. Hence, a system integrator can select which version to use depending on the cost factors at hand. The ETC can make use of an embedded CPU in the Device Under Test (DUT), for performing test on the DUT. For DUTs where no embedded CPU is available, there is the additional cost of a test specific CPU for the ETC. To access the DUT during the test application, the IEEE 1149.1 (JTAG) interface is used. The ETC generates test result that provides information of failing ICs and patterns. The designed and implemented versions of the ETC are validated through experimentations. An FPGA platform is used for experimental validation of the ETC versions. A set of tools are developed for automating the experimental setup. Performance and hardware cost of the ETC versions are evaluated using the ITC'02 benchmarks.